XRT74L73 Datasheet, PDF (6/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
AE4
NAME
INT
AC4
PTYPE0
AD3
PTYPE1
AF3
PTYPE2
TYPE
O
I
DESCRIPTION
Interrupt Request Output:
This open-drain, active-”Low” output signal will be asserted when the UNI/Framer
is requesting interrupt service from the local microprocessor. This output pin
should typically be connected to the “Interrupt Request” input of the local micro-
processor.
Microprocessor Type Select Input:
These three input pins permit the user to configure the Microprocessor Interface
block to readily support a wide variety of Microprocessor Interfaces. The relation-
ship between the settings of these input pins and the corresponding Microproces-
sor Interface configuration is presented below.
AF1
RD_DS
AD1
RDY_DTACK
V2
Reset
AD5
µPClk
PTYPE[2:0]
000
001
010
011
100
101
Microprocessor Interface Mode
Asynchronous Intel
Asynchronous Motorola
Intel X86
Intel I960, Motorola MPC860
IDT3051/52 (MIPS)
IBM Power PC
I
Read Data Strobe (Intel Mode):
If the microprocessor interface is operating in the Intel Mode, then this input will
function as the RD (READ Strobe) input signal from the local µP. Once this
active-”Low” signal is asserted, then the UNI/Framer will place the contents of
the addressed registers (within the UNI/Framer IC) on the Microprocessor Data
Bus (D[7:0]). When this signal is negated, the Data Bus will be tri-stated.
Data Strobe (Motorola Mode):
If the microprocessor interface is operating in the Motorola mode, then this pin will
function as the active-”Low” DS (DATA Strobe) signal.
O
READY or DTACK:
This active-”Low” output pin will function as the READY output, when the micro-
processor interface is running in the Intel Mode; and will function as the DTACK
output, when the microprocessor interface is running in the Motorola Mode.
Intel Mode—READY Output.
When the UNI negates this output pin (e.g., toggles it “Low”), it indicates to the
µP that the current READ or WRITE cycle is to be extended until this signal is
asserted (e.g., toggled “High”).
Motorola Mode:—DTACK (Data Transfer Acknowledge) Output.
The UNI Framer will assert this pin in order to inform the local microprocessor
that the present READ or WRITE cycle is nearly complete. If the UNI/Framer
requires that the current READ or WRITE cycle be extended, then the UNI/
Framer will delay its assertion of this signal. The 68000 family of µPs requires
this signal from its peripheral devices in order to quickly and properly complete a
READ or WRITE cycle.
I
Reset Input:
When this active-”Low” signal is asserted, the UNI/Framer will be asynchro-
nously reset. When this occurs, all outputs will be “tri-stated” and all on-chip reg-
isters will be reset to their default values.
I
Microprocessor Interface Clock Input
This clock input signal is used for synchronous/burst/DMA data transfer opera-
tions. This clock can be running up to 33MHz.
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