XRT74L73 Datasheet, PDF (166/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
FIGURE 39. SIMPLE ILLUSTRATION OF SINGLE-PHY OPERATION
To/From
DS3 LIU
DS3 UNI
TxPOS _{RxUData[15:0]}
TxNEG
RxUClav
TxLineClk
RxUSoC
RxUEn
RxPOS
RxUPrty
RxNEG
RxUClk
RxLineClk
TxUData[15:0]
TxUClav
TxUSoC
TxUEn
TxUPrty
TxUClk
ATM Switch
Rx ATM Cell Data
Rx Flow Control Input
Rx Start of Cell Input
Rx Read Output Enable Signal
Rx Utopia Data Bus Parity
Rx FIFO Clock Signal
Tx ATM Cell Data
Flow Control Input
Start of Cell Output
Tx Write Enable Output
Tx Utopia Data Bus Parity
Tx FIFO Clock Signal
(ATM Layer Device)
This section presents a detailed description of “Single-
PHY” operation. Whenever the ATM Layer processor
is responsible for receiving cell data from the Receive
UTOPIA Interface block, it must do the following.
1. Check the level of the RxUClav pin
If the RxUClav pin is “high” then the RxFIFO contains
some ATM cell data that needs to be read by the ATM
Layer processor. In this case, the ATM Layer proces-
sor should begin to read the cell data from the Receive
UTOPIA Interface block. However, if the RxUClav pin
is “low”, then the RxFIFO does not contain any cell
data that can be read. In this case, the ATM Layer
processor should wait until RxUClav toggles “high”
before attempting to read any more cell data from the
“Receive UTOPIA Interface block”.
Note: The actual meaning associated with RxUClav toggling
“high” or “low” depends upon whether the UNI is operating
in the “Cell Level” or “Octet Level” handshake modes.
2. Assert the RxUEn pin and read the first byte (or word)
of the new cell from the Receive UTOPIA Data Bus.
Once the ATM Layer processor has detected that Rx-
UClav has toggled “high”, then it should assert the
RxUEn input pin (e.g., toggling it “low”). Once the Re-
ceive UTOPIA Interface block has determined that
the RxUEn input pin is “low”, then it will begin to place
some cell data onto the Receive UTOPIA Data Bus. If
this first byte (or word) is the beginning of a new ATM
cell, then the ATM Layer processor should verify that
this byte (or word) is indeed the beginning of a new
cell, by observing the RxUSoC output pin (of the UNI
IC) pulsing “high” for one clock period of RxUClk.
3. Compute the odd-parity of the byte (or word) that is
being read from the Receive UTOPIA Data bus, and
compare the value of this parity bit with that of the
RxUPrty output pin.
This operation is optional, but should be done concur-
rently while checking for the assertion of the RxUSoc
output pin.
When reading in the subsequent bytes (or words) of
the cell, the ATM Layer must do the following.
• Repeat Steps 1 and 2.
• If the UNI is operating in the Octet-Level Hand-
shake mode, then the ATM Layer processor should
check the RxUClav level prior to asserting the
RxUEn (Receive UTOPIA Interface—Output Enable)
pin. The ATM Layer processor should only attempt
to read the contents of the Receive UTOPIA Data
Bus if the RxUClav signal is “high”.
• If the UNI is operating in the Cell-Level Handshake
mode, then the ATM Layer processor should check
the RxUClav signal level just as it (the ATM Layer
processor) is reading in the very last byte (or word)
of a given cell. If the RxUClav level is “high”, then
the ATM Layer processor should proceed to read in
the next cell from the Receive UTOPIA Interface
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