XRT74L73 Datasheet, PDF (253/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
The LAPD receiver’s actions are facilitated via the fol-
lowing two registers.
• Rx DS3 LAPD Control Register
• Rx DS3 LAPD Status Register
Operation of the LAPD Receiver
The LAPD Receiver, once enabled, will begin search-
ing for the boundaries of the incoming LAPD mes-
sage. The LAPD Message Frame boundaries are de-
lineated via the Flag Sequence octets (0x7E), as de-
picted in Figure 92 .
FIGURE 92. LAPD MESSAGE FRAME FORMAT
Flag Sequence (8 bits)
SAPI (6-bits)
TEI (7 bits)
C/R EA
EA
Control (8-bits)
76 or 82 Bytes of Information (Payload)
FCS - MSB
FCS - LSB
Flag Sequence (8-bits)
Where: Flag Sequence = 0x7E
SAPI + CR + EA = 0x3C or 0x3E
TEI + EA = 0x01
Control = 0x03
The 16 bit FCS is calculated using CRC-16, x16 +
x12 + x5 + 1
mation field and the corresponding message type/
size follow:
CL Path Identification = 0x32 (76 bytes)
IDLE Signal Identification = 0x34 (76 bytes)
Test Signal Identification = 0x38 (76 bytes)
ITU-T Path Identification = 0x3F (82 bytes)
The microprocessor/microcontroller (at the remote
terminal), while assembling the LAPD Message
frame, will insert an additional byte at the beginning
of the information (payload) field. This first byte of the
information field indicates the type and size of the
message being transferred. The value of this infor-
The LAPD Receiver must be enabled before it can
begin receiving any LAPD messages. The LAPD Re-
ceiver can be enabled by writing a "1" into Bit 2 (Rx-
LAPD Enable) within the Rx DS3 LAPD Control Reg-
ister. The bit format of this register is depicted below.
RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
BIT 4
Not Used
RO
RO
RO
RO
0
0
0
0
Once the LAPD Receiver has been enabled, it will
begin searching for the Flag Sequence octets (0x7E),
in the DL bit-fields, within the incoming DS3 frames.
When the LAPD Receiver finds the flag sequence
BIT 3
BIT2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
Interrupt
Enable
RxLAPD
Interrupt
Status
RO
R/W
R/W
RUR
0
1
X
X
byte, it will assert the Flag Present bit (Bit 0) within
the Rx DS3 LAPD Status Register, as depicted be-
low.
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