XRT74L73 Datasheet, PDF (67/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
BIT NUMBER
NAME
4
Receive
ATM Cell/PPP Processor
Block Interrupt Enable
3
Transmit
UTOPIA/POS-PHY
Interface Block Interrupt
Enable
2-1
0
Unused
Transmit ATM Cell/PPP
Processor Block
Interrupt Enable
TYPE
R/W
R/W
R/O
R/W
DESCRIPTION
Receive ATM Cell/PPP Processor Block Interrupt Enable:
This READ/WRITE bit permit the user to either enable or disable
the Receive ATM Cell/PPP Processor Block for interrupt genera-
tion. If the user writes a "0" to this register bit and disables the
"Receive ATM Cell/PPP Processor Block" (for interrupt genera-
tion), then all "Receive ATM Cell/PPP Processor Block" inter-
rupts will be disabled for interrupt generation. If the user writes a
"1" to this register bit, he/she will still need to enable the individ-
ual "Receive ATM Cell/PPP Processor Block" interrupt(s) at the
"Source Level" in order to enable that particular interrupt.
0 - Disable all "Receive ATM Cell/PPP Processor Block" inter-
rupts within the device.
1 - Enables the "Receive ATM Cell/PPP Processor Block" at the
"Block-Level".
Transmit UTOPIA/POS-PHY Interface Block Interrupt
Enable:
This READ/WRITE bit permit the user to either enable or disable
the Transmit UTOPIA/POS-PHY Interface Block for interrupt
generation. If the user writes a "0" to this register bit and dis-
ables the "Transmit UTOPIA/POS-PHY Interface Block" (for
interrupt generation), then all "Transmit UTOPIA/POS-PHY
Interface Block" interrupts will be disabled for interrupt genera-
tion. If the user writes a "1" to this register bit, he/she will still
need to enable the individual "Transmit UTOPIA/POS-PHY Inter-
face Block" interrupt(s) at the "Source Level" in order to enable
that particular interrupt.
0 - Disable all "Transmit UTOPIA/POS-PHY Interface Block"
interrupts within the device.
1 - Enables the "Transmit UTOPIA/POS-PHY Interface Block" at
the "Block-Level".
Transmit ATM Cell/PPP Processor Block Interrupt Enable:
This READ/WRITE bit permit the user to either enable or disable
the Transmit ATM Cell/PPP Processor Block for interrupt gener-
ation. If the user writes a "0" to this register bit and disables the
"Transmit ATM Cell/PPP Processor Block" (for interrupt genera-
tion), then all "Transmit ATM Cell/PPP Processor Block" inter-
rupts will be disabled for interrupt generation. If the user writes a
"1" to this register bit, he/she will still need to enable the individ-
ual "Transmit ATM Cell/PPP Processor Block" interrupt(s) at the
"Source Level" in order to enable that particular interrupt.
0 - Disable all "Transmit ATM Cell/PPP Processor Block" inter-
rupts within the device.
1 - Enables the "Transmit ATM Cell/PPP Processor Block" at the
"Block-Level".
CHANNEL INTERRUPT INDICATION REG-
ISTERS
68