XRT74L73 Datasheet, PDF (30/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
Tx Cell Processor
AC16
AE17
AF17
TxCellTxed_0/
TxNibFrame_0/
ValidFCS_0
TxCellTxed_1/
TxNibFrame_0/
ValidFCS_1
TxCellTxed_2/
TxNibFrame_0/
ValidFCS_2
TYPE
DESCRIPTION
O Transmit Cell Generator Indicator/Transmit Nibble Frame Indicator/Valid
FCS Indicator output:
The exact function of this output pin depends upon whether the XRT74L73
device has been configured to operate in the ATM Mode, the Clear-Channel
Framer Mode or in the High-Speed HDLC Controller Mode.
ATM Mode - TxCellTxed_n:
This output pin pulses "high" each time the Transmit Cell Processor transmits a
cell to either the Transmit PLCP Processor or the Transmit DS3/E3 Framer
block.
Clear-Channel Framer Mode - TxNibFrame_n:
This output pin pulses "high" when the last nibble of a given DS3 or E3 frame is
expected at the TxNib_n[2:0] input pins. The purpose of this output pin is to alert
the local terminal equipment that it needs to begin the transmission of a new
DS3 or E3 frame to the XRT74L73 device.
NOTE: This output pin is not active if the channel is configured to operate in the
"Serial-Mode".
High-Speed HDLC Controller Mode - ValidFCS_n:
The combination of the RxIdle_n and ValidFCS_n output signals are used to
convey information about data that is being output via the Receive HDLC Con-
troller output Data bus (RxHDLCDat_[7:0]_n).
If RxIdle = HIGH;
The Receive HDLC Controller block with drive this output pin "high" anytime the
flag sequence octet (0x7E) is present on the "RxHDLCDat_n[7:0]" output data
bus.
If RxIdle_n and ValidFCS_n are both "high"
The Receive HDLC Controller block has received a complete HDLC frame, and
has determined that the FCS value (within this HDLC frame) are valid.
If RxIdle_n is "high" and "ValidFCS_n" is "low"
The Receive HDLC Controller block has received a complete HDLC frame, and
has determined that the FCS value (within this HDLC frame) is invalid.
If "RxIdle_n" is "high" and "ValidFCS_n" is "low"
The Receive HDLC Controller block has received an ABORT sequence.
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