XRT74L73 Datasheet, PDF (108/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
activated by writing a “1” to bit 3 (GFC Insert Enable)
of the “TxCP Control” Register, as depicted below.
TxCP Control Register (Address = 60h)
BIT 7
BIT 6
BIT 5
Scrambler
Enable
Coset Enable
HEC Insert
Enable
R/W
R/W
R/W
1
1
1
BIT 4
TDPChk
Pattern
R/W
1
BIT 3
GFC Insert
Enable
R/W
x
BIT 2
TDPErr Inter-
rupt
Enable
R/W
0
BIT 1
Idle Cell
HEC CalEn
R/W
1
BIT 0
TDPErr Inter-
rupt Status
RUR
0
Once the “Transmit GFC Nibble-field” Serial input port
is activated, it will accept the 4 bit GFC value via the
TxGFC pin during each cell processing period. The
TxGFC serial input port will be expecting the bits of
the GFC nibble-field in descending order (MSB first).
The GFC bits are clocked into the serial input port via
the rising edge of the clock signal, TxGFCClk. Since
these four bits must be provided for each cell; TxG-
FCClk will provide four clock edges during each cell
processing period. The “Transmit GFC Nibble-field”
Serial input port will also provide a “framing pulse” in
the form of the TxGFCMSB output pin pulsing “high”.
This output pin will pulse “high” when the Transmit
Cell Processor is ready to receive the MSB (most sig-
nificant bit) of the GFC field. Figure 17 presents a
timing diagram illustrating the role of each of these
signals during GFC insertion.
FIGURE 17. BEHAVIOR OF TXGFC, TXGFCCLK, AND TXGFCMSB DURING GFC INSERTION INTO THE
“OUTBOUND” CELL
TxGFCClk
TxGFCMSB
TxGFC
t13
t14
t15
t17
t16
BIT 3
BIT 2
BIT 1
BIT 0
6.2.2.4 OAM Cell Processing
The UNI chip provides on-chip RAM space for the
storage of the complete contents (header and pay-
load) of an OAM cell. This RAM space is known as
the “Transmit OAM Cell” buffer (consisting of 54
bytes) and is located at 136h through 16Bh in the UNI
address space. Therefore, in order to “load” the OAM
cell into the “Transmit OAM Cell” buffer, the local µP
must write this data into this address location within
the UNI IC, via the Microprocessor Interface. After-
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