XRT74L73 Datasheet, PDF (90/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
with any further write operations to the Transmit UTOPIA
Interface block. Therefore, the ATM Layer processor pro-
ceeds to write in Words W23 through W26 and then
negates the TxUEn signal after clock edge #28. At this
point, the ATM Layer processor must wait until TxUClav
toggle “high” once again; before writing in the next ATM
cell.
2.1.2.3.1Selecting the Operating Depth of the
TxFIFO
The physical depth of the TxFIFO is 16 cells but can be
operated with a smaller FIFO depth. Therefore, the UNI
allows the selection of operating depths of 4, 8, 12 or
the full 16 cells. This selection can be made by writing
the appropriate data to Bits 1 and 2 (TFIFODepth[1, 0])
within the UTOPIA Configuration Register, as depict-
ed below .
UTOPIA Configuration Register: Address = 6Ah
BIT 7
BIT 6
Unused
RO
BIT 5
Handshake Mode
R/W
BIT 4
M-PHY
R/W
BIT 3
CellOf52 Bytes
R/W
BIT 2
BIT 1
TFIFODepth[1, 0]
R/W
BIT 0
UtWidth16
R/W
The following table presents the values for both Bits 1 and the corresponding operating depth of the
and 2 (within the UTOPIA Configuration Register)
TxFIFO.
TABLE 6: THE RELATIONSHIP BETWEEN TXFIFODEPTH[1:0] WITHIN THE UTOPIA CONFIGURATION REGISTER
AND THE OPERATING DEPTH OF THE TXFIFO
BIT 2
0
0
1
1
BIT 1
0
1
0
1
OPERATING DEPTH OF THE TRANSMIT FIFO
16 cells
12 cells
8 cells
4 cells
The operating depth of the Transmit FIFO will be 16
cells upon power up or reset. Therefore, the appropri-
ate data must be written to these two bit-fields in or-
der to change this parameter.
2.1.2.3.2Resetting the TxFIFO via Software Com-
mand
The UNI allows the TxFIFO to be reset via software
command, without the need to implement a master
reset of the entire UNI device. This can be
accomplished by writing the appropriate data to bit 7
(TxFIFO Reset) of the Transmit UTOPIA Interrupt
Enable/Status Register as depicted below.
Transmit UTOPIA—Interrupt/Status Register (Address—6Eh)
BIT 7
BIT 6
TFIFO Reset
Discard Upon
PErr
R/W
R/W
BIT 5
TPerr IntEn
R/W
BIT 4
TFIFO
ErrIntEn
R/W
BIT 3
BIT 2
TCOCA IntEn TPErr IntStat
R/W
RUR
BIT 1
TFIFO
OverInt Stat
RUR
BIT 0
TCOCA
IntStat
RUR
2.1.2.3.3Monitoring the TxFIFO Status
The local µP has the ability to poll and monitor the
status of the TxFIFO via the Transmit UTOPIA FIFO
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