XRT74L73 Datasheet, PDF (23/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PIN DESCRIPTION
PIN#
NAME
Tx PLCP Processor
G1
TxNib_1_0/
Tx8KRef_0/
TxHDLCDat_1_0
H3
TxNib_1_1/
Tx8KRef_1/
TxHDLCDat_1_1
H2
TxNib_1_2/
Tx8KRef_2/
TxHDLCDat_1_2
TYPE
DESCRIPTION
I
Transmit Nibble Input Interface - Bit 1/Transmit PLCP Framing 8kHz Refer-
ence Input/Transmit HDLC Controller Data Bus - Bit 1 Input:
The exact function of this input pin depends upon whether the XRT74L73 device
is configured to operate in the Clear-Channel Framer Mode, the High-Speed
HDLC Controller Mode, or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_1_n:
If the user opts to operate the XRT74L73 device in the Nibble-Parallel Mode,
then this input pin will function as the bit 1 input to the "Transmit Nibble-Parallel"
input interface. The Transmit Payload Data Input Interface block will sample this
signal (along with TxNib_0_n, TxNib_2_n and TxNib_3_n) upon the falling edge
of TxNibClk_n
NOTE: This input pin is inactive if the Channel is configured to operate in the
"Serial" Mode.
ATM/PLCP Mode - Tx8KREF_n:
If the XRT74L73 is configured to operate in the ATM/PLCP Mode, then the
Transmit PLCP Processor can be configured to synchronize its PLCP frame
generation to this input clock signal. The Transmit PLCP Processor will also
use this input signal to compute the nibble-trailer stuff opportunities.
NOTE: This input pin is inactive if the use has configured the XRT74L73 device
to operate in the "Direct-Mapped" ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_1_n:
If the channel is configured to operate in the High-Speed HDLC Controller mode,
then the local terminal equipment will be provided with a "byte-wide" Transmit
HDLC Controller byte-wide input interface. This input pin will function as "Bit 1"
within this byte wide interface. Data, residing on the "Transmit HDLC Controller"
byte wide input interface, will be sampled upon the rising edge of the
TxHDLCClk_n output signal.
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