XRT74L73 Datasheet, PDF (39/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PIN DESCRIPTION
PIN#
NAME
Rx UTOPIA Interface
AD22
AF21
AE21
AC20
AF20
RxUAddr0
RxUAddr1
RxUAddr2
RxUAddr3
RxUAddr4
AE18
RxUClav/
RxPPA
AD17
RxUClk/
RxPClk
TYPE
DESCRIPTION
I
Receive UTOPIA Address Bus input (MSB):
These input pins functions as the Receive UTOPIA Address bus inputs. These
input pins are only active when the Framer/UNI device is operating in the ATM
UNI Mode. The Receive UTOPIA Address Bus input is sampled on the rising
edge of the RxClk signal. The contents of this address bus are compared with
the value stored in the "Rx UT Address Register (Address = 0x6C). If these two
values match, then the UNI will inform the ATM Layer Processor on whether or
not it has any new ATM cells to be read from the RxFIFO; by driving the RxClav
output to the appropriate level. If these two address values do not match, then
the UNI will not respond to the ATM Layer Processor; and will keep its RxClav
output signal tri-stated.
O Receive UTOPIA - Cell Available/Receive POS-PHY Interface - Packet Avail-
able:
The exact function of this output pin depends upon whether the XRT74L73
device has been configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode - RxUClav
The Receive UTOPIA Interface block will assert this output pin in order to indi-
cate that the Rx FIFO has some ATM cell data that needs to be read by the ATM
Layer Processor. This signal is asserted if the RxFIFO contains at least one full
cell of data. This signal toggle "low" if the RxFIFO is depleted of data, or if it con-
tains less than one full cell of data.
Multi-PHY Operation:
When the UNI chip is operating in the Multi-PHY mode, this signal will be tri-
stated until the RxClk cycle following the assertion of a valid address on the
Receive UTOPIA Address bus input pins (e.g., if the contents on the Receive
UTOPIA Address bus pins match that with the Receive UTOPIA Address Regis-
ter). Afterwards, this output pin will behave in accordance with the cell-level
handshake mode.
PPP Mode - RxPPA
The XRT74L73 device will pulse this output pin "high" whenever a (programma-
ble) number of bytes are available to be read from the RxFIFO.
I
Receive UTOPIA Interface Clock Input/Receive POS-PHY Interface Clock
Input:
The exact function of this input pin depends upon whether the XRT74L73 device
is operating in the ATM UNI or PPP Mode.
ATM UNI Mode - RxUClk
The byte (or word) data, on the Receive UTOPIA Data bus (RxUData[15:0]) is
updated on the rising edge of this signal. The Receive UTOPIA Interface can be
clocked at rates up to 50 MHz.
PPP Mode - RxPClk
This byte (or word) data, on the Receive POS-PHY Data Bus (RxPData[15:0]) is
updated on the rising edge of this signal. The Receive POS-PHY Interface can
be clocked at rates up to 50MHz.
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