XRT74L73 Datasheet, PDF (10/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
D20
B19
A19
NAME
REQ_EN_0
REQ_EN_1
REQ_EN_2
P23
RLOL_0
N24
RLOL_1
N25
RLOL_2
A15
RLOOP_0
B14
RLOOP_1
A14
RLOOP_2
TYPE
O
I
O
DESCRIPTION
Receive Equalization Bypass Control Output Pin—(to be connected to the
XRT73L03 E3/DS3/STS-1 LIU IC):
This output pin is intended to be connected to the REQEN input pin of the
XRT73L03 E3/DS3/STS-1 LIU IC. The user can control the state of this output pin
by writing a ‘0’ or ‘1’ to Bit 5 (REQEN) of the Line Interface Driver Register
(Address = 0xXX, 0xXX). If the user commands this signal to toggle “High” then it
will cause the incoming DS3 line signal to “by-pass” equalization circuitry, within
the XRT73L03 Device. Conversely, if the user commands this output signal to
toggle “Low”, then the incoming DS3 line signal with be routed through the equal-
ization circuitry. For information on the criteria that should be used when deciding
whether to bypass the equalization circuitry or not, please consult the
“XRT73L03 E3/DS3/STS-1 LIU IC” data sheet.
Writing a “1” to Bit 5 of the Line Interface Drive Register will cause this output pin
to toggle “High”. Writing a “0” to this bit-field will cause this output pin to toggle
“Low”.
NOTE: If the designer is not using the XRT73L03 E3/DS3/STS-1 LIU IC, then
this output pin can be used for other purposes.
Receive Loss of Lock Indicator—from the XRT73L03 E3/DS3/STS-1 LIU IC:
This input pin is intended to be connected to the RLOL (Receive Loss of Lock)
output pin of the XRT73L03 LIU IC. The user can monitor the state of this pin by
reading the state of Bit 1 (RLOL) within the Line Interface Scan Register
(Address = 0xXX, 0xXX).
If this input pin is "low" it means that the Clock Recovery PLL (within the corre-
sponding channel of the XRT73L03 device) is properly locked onto and is per-
forming clock and data recovery on the "incoming" DS3 or E3 data stream. If this
input pin is "high" then it means the Clock Recovery PLL is NOT properly locked
onto the incoming DS3 or E3 line signal. Further, this indicates that the Clock
Recovery PLL is NOT performing clock and data recovery on this incoming DS3
or E3 data stream.
For more information on the operation of the XRT73L03 E3/DS3/STS-1 LIU IC,
please consult the "XRT73L03 E3/DS3/STS-1 LIU IC" data sheet.
NOTE: If the designer is not using the XRT73L03 DS3/E3/STS-1 LIU IC, this
input pin can be used for other purposes.
Remote Loop-back Output Pin (to the XRT73L03 DS3/E3/STS-1 LIU IC):
This output pin is intended to be connected to the RLOOP input pin of the
XRT73L03 LIU IC. This output pin, along with the LLOOP input pin permits the
user to configure the XRT73L03 to operate in either of the following three (3) loop-
back modes.
• Analog Local Loop-Back Mode
• Digital Local Loop-Back Mode
• Remote Loop-Back Mode.
For a detailed description on how to configure the XRT73L03 to operate in each
of these loop-back modes, please see Section _.
Writing a “1” to bit 1 of the “Line Interface Drive Register (Address = 0x72) will
cause this output pin to toggle “High”. Writing a “0” to this bit-field will cause the
RLOOP output to toggle “Low”.
NOTE: If the customer is not using the XRT73L03 DS3/E3/STS-1 IC, then this
output pin can be used for other purposes.
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