XRT74L73 Datasheet, PDF (175/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
The RxUT Interrupt Enable/Status Register has eight
bit-fields. However, only six of these bit-fields are rel-
evant to interrupt processing. Bits 0–2 are the inter-
rupt status bits and bits 3–5 are the interrupt enable
bits for the Receive UTOPIA Interface block. Each of
these “interrupt processing relevant” bit-fields are de-
fined below.
Bit 0–—RCOCA Interrupt Status—Receive UTOPIA
Change of Cell Alignment Condition
If the RxFIFO Manager detects a “runt” cell, then it
will generate the “Receive UTOPIA Change of Cell
Alignment Condition” interrupt, and the “runt” cell will
be discarded. The Receive UTOPIA Interface block
will indicate that it is generating this kind of interrupt
by asserting Bit 0 (RCOCA Interrupt Status) of the
Receive UTOPIA Interrupt Enable/Status Register, as
depicted below.
Address = 6Bh, RxUT Interrupt Enable/Status Register
BIT 7
Unused
RO
0
BIT 6
BIT 5
RxFIFO
RxFIFO Reset Overflw Inter-
rupt Enable
R/W
R/W
0
x
BIT 4
RxFIFO
Underflw
Interrupt
Enable
R/W
x
BIT 3
RCOCA
Interrupt
Enable
R/W
1
BIT 2
RxFIFO
Overflw Inter-
rupt
Status
RUR
x
BIT 1
RxFIFO
Underflw
Interrupt
Status
RUR
x
BIT 0
RCOCA
Interrupt
Status
RUR
1
Bit 1—RxFIFO Underflw Interupt Status—RxFIFO
Underrun Condition
Whenever the Receive UTOPIA Interface block sets
its RxUClav signal to “high”, the ATM Layer processor
will know that the RxFIFO has some ATM cell data
that needs to be read. Hence, the ATM Layer processor
will begin to read out this cell data. If the ATM Layer
processor reads out all of the cell data and depletes
the RxFIFO, then the UNI will generate an “RxFIFO
Underrun” Interrupt. The Receive UTOPIA Interface
block will indicate that it is generating this kind of
interrupt by asserting Bit 1 (RxFIFO Underflw Inter-
rupt Status) of the Receive UTOPIAn Interrupt
Enable/Status Register, as depicted below.
Address = 6Bh, RxUT Interrupt Enable/Status Register
BIT 7
Unused
RO
0
BIT 6
BIT 5
RxFIFO
RxFIFO Reset Overflw Inter-
rupt Enable
R/W
R/W
0
x
BIT 4
RxFIFO
Underflw
Interrupt
Enable
R/W
1
BIT 3
RCOCA
Interrupt
Enable
R/W
x
BIT 2
RxFIFO
Overflw Inter-
rupt
Status
RUR
x
BIT 1
RxFIFO
Underflw
Interrupt
Status
RUR
1
BIT 0
RCOCA
Interrupt
Status
RUR
x
Bit 2—RxFIFO Overflw Interrupt Status—RxFIFO
Overrun Condition
If the RxFIFO is filled to capacity, and if the ATM Layer
processor is unable to begin reading its contents
before the Receive Cell Processor writes another cell
into the RxFIFO, some of the data within the RxFIFO
will be overwritten, and in turn lost. If the Receive
UTOPIA Interface block detects this condition, and if
this interrupt condition has been enabled then the
UNI will assert the INT* pin to the local µP/µC. Addi-
tionally, the UNI will set bit 2, within the Receive UTO-
PIA Interrupt Enable/Status Register to “1” as depict-
ed below.
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