XRT74L73 Datasheet, PDF (339/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
5.3.1.2.3 Line Code Violations
The Receive E3 LIU Interface block will also check
the incoming E3 data stream for line code violations.
For example, when the Receive E3 LIU Interface
block detects a valid bipolar violation (e.g., in HDB3
line code), it will substitute four zeros into the binary
data stream. However, if the bipolar violation is in-
valid, then an LCV (Line Code Violation) is flagged
and the PMON LCV Event Count Register (Address =
0x50 and 0x51) will also be incremented. Additional-
ly, the LCV-One-Second Accumulation Registers (Ad-
dress = 0x6E and 0x6F) will be incremented. For ex-
ample: If the incoming E3 data is HDB3 encoded, the
Receive E3 LIU Interface block will also increment
II/O CONTROL REGISTER (ADDRESS = 0X01)
the LCV One-Second Accumulation Register if three
(or more) consecutive zeros are received.
5.3.1.2.4 RxLineClk Clock Edge Selection
The incoming unipolar or bipolar data, applied to the
RxPOS and the RxNEG input pins are clocked into
the Receive E3 LIU Interface block via the RxLineClk
signal. The Framer IC allows the user to specify
which edge (e.g, rising or falling) of the RxLineClk
signal will sample and latch the signal at the RxPOS
and RxNEG input signals into the Framer IC. The us-
er can make this selection by writing the appropriate
data to bit 1 of the I/O Control Register, as depicted
below.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Disable
TxLOC
LOC
Disable AMI/ZeroSup* Unipolar/
RxLOC
Bipolar*
TxLine CLK RxLine CLK
Invert
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
0
Table 76 depicts the relationship between the value
of this bit-field to the sampling clock edge of RxLi-
neClk.
TABLE 76: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL
REGISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL
RXCLKINV
(BIT 1)
RESULT
0 .Rising Edge:
RxPOS and RxNEG are sampled at the rising edge of RxLineClk. See Figure 140 for timing relationship
between RxLineClk, RxPOS, and RxNEG.
1 Falling Edge:
RxPOS and RxNEG are sampled at the falling edge of RxLineClk. See Figure 141 for timing relationship
between RxLineClk, RxPOS, and RxNEG.
Figure 140 and Figure 141 present the Waveform
and Timing Relationships between RxLineClk, Rx-
POS and RxNEG for each of these configurations.
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