XRT74L73 Datasheet, PDF (16/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
D3
D2
E3
NAME
TxOHFrame_0/
TxHDLCClk_0
TxOHFrame_1/
TxHDLCClk_1
TxOHFrame_2/
TxHDLCClk_2
A3
TxOHIns_0/
TxHDLCDat_4_0
A1
TxOHIns_1/
TxHDLCDat_4_1
B2
TxOHIns_2/
TxHDLCDat_4_2
TYPE
O
I
DESCRIPTION
Transmit Overhead Framing Pulse/Transmit HDLC Controller Clock Output
pin:
The function of this output pin depends upon whether the channel (within the
XRT74L73 device) has been configured to operate in the "High-Speed HDLC
Controller" Mode or not.
Non-High-Speed HDLC Controller Mode - TxOHFrame_n:
This output pin pulses high for one TxOHClk_n period coincident with the instant
the Transmit Overhead Data Input Interface would be accepting the first over-
head bit within an outbound DS3 or E3 frame.
High Speed HDLC Controller Mode - TxHDLCClk_n:
This output pin functions as the "demand" clock output signal for the "Transmit
HDLC Controller" byte-wide input interface. This clock signal is ultimately
derived from either the TxInClk_n or the RxOutClk_n signal. Hence, the fre-
quency of this clock signal is nominally one-eight of that of the TxInClk_n or the
RxOutClk_n signals. The Transmit HDLC Controller block will sample the con-
tents of the "Transmit HDLC Controller" byte-wide input interface upon the rising
edge of this clock output signal. Therefore, the local terminal equipment should
be designed to output data (onto the TxHDLCDat[7:0] bus) upon the falling edge
of this clock output signal.
Transmit Overhead Data Insert Input:
Transmit Overhead Data Insert Input/Transmit HDLC Controller Data Bit 4 input
pin:The function of these input pins depends upon whether the channel (within
the XRT74L73 device) has been configured to operate in the "High-Speed HDLC
Controller" Mode or not.
Non-High Speed HDLC Controller Mode - TxOHIns_n:
This input pin permits the user to either enable or disable the "Transmit Over-
head Data Input Interface" block. If the Transmit Overhead Data Input Interface
block is enabled, then it will accept overhead data (from the local terminal equip-
ment) via the "TxOH_n" input pin; and insert this data into the overhead bit posi-
tions within the outbound DS3 or E3 data stream. Conversely, if the Transmit
Overhead Data Input Interface block is disabled, then it will NOT accept over-
head data from the local terminal equipment .Pulling this input pin "high" enables
the "Transmit Overhead Data Input Interface" block. Pulling this input pin "low"
disables the "Transmit Overhead Data Input Interface" block.
High-Speed HDLC Controller Mode - TxHDLCDat_4_n:
If the channel is configured to operate in the High-Speed HDLC Controller mode,
then the local terminal equipment will be provided with a "byte-wide" Transmit
HDLC Controller byte-wide input interface. This input pin will function as "Bit 4"
within this byte wide interface. Data, residing on the "Transmit HDLC Controller"
byte wide input interface, will be sampled upon the rising edge of the
TxHDLCClk_n output signal.
17