XRT74L73 Datasheet, PDF (281/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
(AIC Interrupt Enable) within the RxDS3 Interrupt En-
able Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change of State on Receive AIC In-
terrupt
Whenever the XRT74L73 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request Output pin (INT)
by driving it "High".
• It will set Bit 2 (AIC Interrupt Status), within the Rx
DS3 Interrupt Status Register, to “1”, as indicated
below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
1
0
0
Whenever the Terminal Equipment encounters this
interrupt, it should do the following.
• It should continue to check the state of the AIC bit,
in order to see if this change is constant.
• If this change is constant, then the user should con-
figure the XRT74L73 Framer IC to operate in the
M13 framing format, if the AIC bit-field is “0”.
• Conversely, if the AIC bit-field is “1”, then the user
should configure the XRT74L73 Framer IC to oper-
ate in the C-bit Parity framing format.
4.3.6.2.7 The Detection of P-Bit Error Interrupt
If the Detection of P-Bit Error Interrupt is enabled,
then the XRT74L73 Framer IC will generate an inter-
rupt, anytime the Receive DS3 Framer block has de-
tected a P-bit error, within the incoming DS3 data
stream.
Enabling and Disabling the Detection of P-Bit Er-
ror Interrupt:
The Detection of P-Bit Error Interrupt can be enabled
or disabled by writing the appropriate value into Bit 0
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