XRT74L73 Datasheet, PDF (250/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
also be configured to receive both types of message
from the remote terminal equipment.
Both BOS and MOS types of HDLC message pro-
cessing are discussed in detail below.
4.3.3.1 Bit-Oriented Signaling (or FEAC) Pro-
cessing via the Receive DS3 HDLC Controller.
The Receive DS3 HDLC Controller block consists of
two major sub-blocks
• The Receive FEAC Processor
• The LAPD Receiver
This section describes how to operate the Receive
FEAC Processor.
If the Receive DS3 Framer block is operating in the
C-bit Parity Framing format, then the FEAC bit-field
within the DS3 Frame can be used to receive FEAC
(Far End Alarm and Control) messages (See
Figure 91 ). Each FEAC code word is actually six bits
in length. However, this six bit FEAC Code word is
encapsulated with 10 framing bits to form a 16 bit
message of the form:
FEAC CODE WORD
FRAMING
0
d5 d4 d3 d2 d1 d0
0
1
1
1
1
1
1
1
1
Where, [d5, d4, d3, d2, d1, d0] is the FEAC Code
word. The rightmost bit of the 16-bit data structure
(e.g., a 1) will be received first. Since each DS3
Frame contains only 1 FEAC bit-field, 16 DS3
Frames are required to transmit the 16 bit FEAC code
message. The six bits, labeled “d5” through “d0” can
represent 64 distinct messages, of which 43 have
been defined in the standards.
The Receive FEAC Processor frames and validates
the incoming FEAC data from the remote Transmit
FEAC Processor via the received FEAC channel.
Additionally, the Receive FEAC Processor will write
the Received FEAC code words into an 8 bit Rx-
FEAC register. Framing is performed by looking for
two 0s spaced 6 bits apart preceded by 8 1s. The Re-
ceive DS3 HDLC Controller contains two registers
that support FEAC Message Reception.
• Rx DS3 FEAC Register (Address = 0x16)
• Rx DS3 FEAC Interrupt Enable/Status Register
(Address = 0x17)
The Receive FEAC Processor generates an interrupt
upon validation and removal of the incoming FEAC
Code words.
The Receive FEAC Processor will validate or remove
FEAC code words that it receives from the remote
Transmit FEAC Processor. The FEAC Code Valida-
tion and Removal functions are described below.
FEAC Code Validation
When the remote terminal equipment wishes to send
a FEAC message to the Local Receive FEAC Pro-
cessor, it (the remote terminal equipment) will trans-
mit this 16 bit message, repeatedly for a total of 10
times. The Receive FEAC Processor will frame to
this incoming FEAC Code Message, and will attempt
to validate this message. Once the Receive FEAC
Processor has received the same FEAC code word in
at least 8 out of the last 10 received codes, it will vali-
date this code word by writing this 6 bit code word in-
to the Receive DS3 FEAC Register. The Receive
FEAC Processor will then inform the µC/µP of this
Receive FEAC validation event by generating a Rx
FEAC Valid interrupt and asserting the FEAC Valid
and the RxFEAC Valid Interrupt Status Bits in the Rx
DS3 Interrupt Enable/Status Register, as depicted
below. The Bit Format of the Rx DS3 FEAC Register
is presented below.
Operation of the Receive DS3 FEAC Processor
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
BIT 4
FEAC
Valid
RO
RO
RO
RO
X
X
X
1
The bit-format of the Rx DS3 FEAC register is pre-
sented below. It is important to note that the last vali-
BIT 3
BIT2
BIT 1
BIT 0
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
status
RxFEAC
Valid
Interrupt
Enable
RxFEAC
Valid
Interrupt
Status
R/W
RUR
R/W
RUR
X
0
1
1
dated FEAC code word will be written into the shaded
bit-fields below.
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