XRT74L73 Datasheet, PDF (83/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT UTOPIA BLOCK
Microprossor
Interface
A[8:0]
D[15:0]
Controls from
Registers
TxFRdClk
TRdEn
TxUClk
TxUSoC
TxUEn
TxUAddr [4:0]
TxUData [15:0]
TxUData [7:0]
TxUtopia
Registers
Control Signals
Status Signals
Tx Utopia
Cell FIFO
TxUData [7:0]
TxUSoC
To Tx Cell Processor
Tx Utopia
FIFO Manager
TxCel Present (to Tx Cell Processor
TxUClav (To Pin)
Status Bits to Registers
TxUtopia Interrupt (To Interrupt block)
The following sections discuss each functional
sub-block of the Transmit UTOPIA Interface Block in
detail. These sections will discuss the many features
associated with the Transmit UTOPIA Interface block
as well as how to select/configure these features in
order to suit particular application needs. Detailed
discussion of Single-PHY and Multi-PHY operation
will each be presented in its own section even though
it involves the use of all of these functional blocks.
2.1.2.1Transmit UTOPIA Bus Input Interface
The Transmit UTOPIA input interface complies with
UTOPIA Level 2 standard interface (e.g., the Transmit
UTOPIA can support both Single-PHY and Multi-PHY
operations.) Additionally, the UNI provides the option
of varying the following features associated with the
Transmit UTOPIA Bus Interface.
• Transmit UTOPIA Data Bus width of 8 or 16 bits
• The cell size (e.g., the number of octets being
processed per cell via the UTOPIA bus)
• The handling of errored cells received from the
ATM Layer processor
A discussion of the operation of the Transmit UTOPIA Bus
Interface along with each of these options will be presented
below.
2.1.2.1.1The Pins of the Transmit UTOPIA Bus
Interface
The ATM Layer processor will interface to the Transmit
UTOPIA Interface block via the following pins.
• TxUData[15:0]—Transmit UTOPIA Data Bus Input
pins
• TxUAddr[4:0]—Transmit UTOPIA Address Bus
Input pins
• TxUClk—Transmit UTOPIA Interface block clock
input pin
• TxUSoC—Transmit “Start of Cell” indicator input
pin
• TxUPrty—Transmit UTOPIA—Odd Parity Input pin
• TxUEn—Transmit UTOPIA Data Bus—Write
Enable input pin
• TxUClav—TxFIFO Cell Available
Each of these signals are briefly discussed below.
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