XRT74L73 Datasheet, PDF (7/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
AC2
WR_R/W
P4
BLAST
U4
DBEN
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
I
I
I
DESCRIPTION
Write Data Strobe (Intel Mode):
If the microprocessor interface is operating in the Intel Mode, then this active-
”Low” input pin functions as the WR (Write Strobe) input signal from the µP.
Once this active-”Low” signal is asserted, then the UNI/Framer will latch the con-
tents of the µP Data Bus ([D:[7:0]) into the addressed register (or RAM location)
within the UNI/Framer IC.
R/W Input Pin (Motorola Mode):
When the Microprocessor Interface Section is operating in the “Motorola Mode”,
then this pin is functionally equivalent to the R/W pin. In the Motorola Mode, a
“READ” operation occurs if this pin is at a logic “1”. A WRITE operation occurs if
this pin is at a logic “0”.
Last Burst Transfer Indicator input pin:
If the Microprocessor Interface is operating in the Intel-I960 Mode, then this input
pin is used to indicate (to the Microprocessor Interface block) that the current
data transfer is the last data transfer within the current burst operation.The
Microprocessor should assert this input pin (by toggling it "Low") in order to
denote that the current READ or WRITE operation (within a BURST operation) is
the last operation of this BURST operation.
Bi-directional Data Bus Enable Input pin:
If the Microprocessor Interface is operating in the Intel-I960 Mode, then this input
pin is used to enable the Bi-directional Data Bus.
Setting this input pin "Low" enables the Bi-directional Data bus. Setting this input
"High" tri-states the Bi-directional Data Bus.
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