XRT74L73 Datasheet, PDF (121/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TxPLCP G1 Byte Register (Address = 4Bh)
BIT 7
RO
BIT 6
Unused
RO
BIT 5
RO
BIT 4
TxPLCP FEBE Mask
R/W
BIT 3
Yellow Alarm
R/W
BIT 2
LSS(2)
R/W
BIT 1
LSS(1)
R/W
BIT 0
LSS(0)
R/W
Writing a ‘1’ to this bit-field will cause the Transmit
PLCP Processor to transmit G1 bytes with the FEBE
nibble value of ‘0h’ (independent of the number of
BIP-8 errors detected by the Receive PLCP Processor).
Writing a ‘0’ to this bit-field will cause the Transmit
PLCP Processor to transmit G1 bytes with the correct
FEBE count, as determined by the “Near-End” Re-
ceive PLCP Processor.
2.3.3.6Forcing a Yellow Alarm—Via Software Con-
trol
The UNI allows for the generation a “Yellow Alarm
(PLCP Version thereof)” via software control. In this
case, the Transmit PLCP Processor will generate a
“Yellow Alarm” by automatically setting the “RAI” bit
within each G1 byte to ‘1’. This option can be exer-
cised by writing the appropriate bit to bit-field 3 of the
TxPLCP G1 Byte Register (Address = 4Bh). The bit
format of this register follows.
TxPLCP G1 Byte Register (Address = 4Bh)
BIT 7
RO
BIT 6
Unused
RO
BIT 5
RO
BIT 4
TxPLCP FEBE Mask
R/W
BIT 3
Yellow Alarm
R/W
BIT 2
LSS(2)
R/W
BIT 1
LSS(1)
R/W
BIT 0
LSS(0)
R/W
Writing a ‘1’ to this bit-field forces the “PLCP—Yellow
Alarm” condition. Writing a ‘0’ to this bit-field allows
the state of the RAI bit to be based upon the framing
conditions of the “Near-End” Receive PLCP Processor.
2.3.3.7Transmitting Data Link Messages via the
G1 Byte
The “TxPLCP G1 Byte” Register contains three bit-
fields that can be used to support a 24 kbps data link
between the Near-End Transmit PLCP Processor,
and the Far-End Receive PLCP Processor, as depicted
below.
TxPLCP G1 Byte Register (Address = 4Bh)
BIT 7
RO
BIT 6
Unused
RO
BIT 5
RO
BIT 4
TxPLCP FEBE Mask
R/W
BIT 3
Yellow Alarm
R/W
BIT 2
LSS(2)
R/W
BIT 1
LSS(1)
R/W
BIT 0
LSS(0)
R/W
Whatever data is written into the three bit-fields will
appear in Bits 2–0 of the incoming G1 byte at the Far-
End Receive PLCP Processor.
2.3.3.8Inserting POH Bytes via the TxPOH Serial
Input Port
The UNI allows the users to externally insert their
own PLCP POH (Path Overhead) bytes via a serial
input interface consisting of the pins: TxPOHIns, Tx-
POH, TxPOHFrame, and TxPOHClk. This serial input
port can be activated by asserting the TxPOHIns in-
put pin (e.g., setting it “high”). When this pin is “low”,
the UNI will internally generate the POH bytes. How-
ever, when this pin is “high”, the users will be expect-
ed to provide their own value for the POH bytes via
the TxPOH input pin. The UNI will assert (toggle
“high”) the TxPOHFrame output pin when it expects
the MSB of the Z6 byte. The users will be expected to
provide their value for the Z6 byte, with the MSB first,
in descending order. Immediately after the LSB of the
Z6 byte, the TxPOH Serial Input port will be expecting
the MSB of the Z5 byte, and so on. The byte order
that this serial input port expects is as presented in
Table 16 . Once the TxPOH serial input port has read
in the LSB of the C1 byte, it will repeat this sequence
of bytes, beginning with the Z6 byte first. The POH
data will be serially latched into the TxPOH input on
the rising edge of the TxPOHClk output signal. The
122