XRT74L73 Datasheet, PDF (243/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
When the µP/µC reads these registers, it will read in
the number of framing bit errors that have been de-
tected since the last read of these two registers.
These registers are reset upon read.
4.3.2.5 DS3 Receive Alarms
The Receive DS3 Framer block is capable of detect-
ing any of the following alarm conditions.
• LOS (Loss of Signal)
• AIS (Alarm Indication Signal)
• The Idle Pattern.
• FERF (Far-End Receive Failure) of Yellow Alarm
condition.
• FEBE (Far-End-Block Error)
• Change in AIC State
The methods by which the Receive DS3 Framer
block uses to detect and declare each of these alarm
conditions are described below.
4.3.2.5.1 The Loss of Signal (LOS) Alarm
The Receive DS3 Framer block will declare a Loss of
Signal (LOS) state when it detects 180 consecutive
incoming “0s” via the RxPOS and RxNEG input pins
or if the RLOS input pin (from the XRT7300 DS3 LIU
or the XRT7295 Line Receiver IC) is asserted (e.g.,
driven "High"). The Receive DS3 Framer block will
indicate the occurrence of an LOS condition by:
1. Asserting the RxLOS output pin (e.g., toggles it
"High").
2. Setting Bit 6 (RxLOS) within the Rx DS3 Configu-
ration and Status Register to 1, as depicted
below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
RxAIS
RxLOS
RxIdle
RxOOF
Int LOS
Disable
Framing on F-Sync Algo M-Sync Algo
Parity
RO
RO
RO
RO
R/W
R/W
R/W
R/W
0
1
0
1
x
x
x
x
3. The Receive DS3 Framer block will generate a
Change in LOS Status interrupt request.
NOTE: The Receive DS3 Framer will also declare an OOF
condition and perform all of the notification procedures as
described in Section 4.3.2.2.
4. Force the on-chip Transmit Section to transmit a
FERF (Far-End Receive Failure) indicator back
out to the remote terminal.
The Receive DS3 Framer block will clear the LOS
condition when at least 60 out of 180 consecutive re-
ceived bits are 1.
NOTE: The Receive DS3 Framer block will also generate
the Change in LOS Condition interrupt, when it clears the
LOS Condition.
The Framer chip allows the user to modify the LOS
Declaration criteria such that an LOS condition is de-
clared only if the RLOS input pin (from the XRT7300
DS3/E3/STS-1 LIU IC) is asserted. In this case, the
internally-generated LOS criteria of 180 consecutive
0s will be disabled. This can be accomplished by
writing a "1" to bit 3 (Int LOS Disable) of the Rx DS3
Configuration and Status Register, as depicted below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
RxAIS
BIT 6
RxLOS
BIT 5
RxIdle
BIT 4
RxOOF
RO
RO
RO
RO
X
X
X
X
NOTE: For more information on the RLOS input pin, please
see Section 2.1.
4.3.2.5.2 The Alarm Indication Signal (AIS)
The Receive DS3 Framer block will identify and de-
clare an AIS condition if it detects all of the following
conditions in the incoming DS3 Data Stream:
BIT 3
BIT2
BIT 1
BIT 0
Int LOS
Disable
Framing on F-Sync Algo M-Sync Algo
Parity
R/W
R/W
R/W
R/W
1
X
X
X
• Valid M-bits, F-bits and P-bits
• All C-bits are zeros.
• X-bits are set to 1
• The Payload portion of the DS3 Frame exhibits a
repeating 1010... pattern.
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