XRT74L73 Datasheet, PDF (475/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
RxDS3/E3
Interrupt
Enable
R/W
X
BIT 6
RO
0
BIT 5
RO
0
BIT 4
Not Used
RO
0
BIT 3
RO
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One-Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Receive Sec-
tion at the Block Level) for interrupt generation. Con-
versely, setting this bit-field to “0” disables the Re-
ceive Section for interrupt generation.
6.3.6.2 Enabling/Disabling and Servicing Inter-
rupts
As mentioned earlier, the Receive Section of the
XRT74L73 Framer IC contains numerous interrupts.
The Enabling/Disabling and Servicing of each of
these interrupts is described below.
6.3.6.2.1 The Change in Receive LOS Condi-
tion Interrupt
If the Change in Receive LOS Condition Interrupt is
enabled, then the XRT74L73 Framer IC will generate
an interrupt in response to either of the following con-
ditions.
1. When the XRT74L73 Framer IC declares an LOS
(Loss of Signal) Condition, and
2. When the XRT74L73 Framer IC clears the LOS
condition.
Conditions causing the XRT74L73 Framer IC to
declare an LOS Condition.
• If the XRT7300 LIU IC declares an LOS condition,
and drives the RLOS input pin (of the XRT74L73
Framer IC) “High”.
• If the XRT74L73 Framer IC detects 32 consecutive
“0”, via the RxPOS and RxNEG input pins.
Conditions causing the XRT74L73 Framer IC to
clear the LOS Condition.
• If the XRT7300 LIU IC clears the LOS condition and
drives the RLOS input pin (of the XRT74L73
Framer IC) “Low”.
• If the XRT74L73 Framer IC detects a string of 32
consecutive bits (via the RxPOS and RxNEG input
pins) that does NOT contain a string of 4 consecu-
tive “0’s”.
Enabling and Disabling the Change in Receive
LOS Condition Interrupt
The user can enable or disable the Change in Re-
ceive LOS Condition Interrupt, by writing the appror-
priate value into Bit 1 (LOS Interrupt Enable), within
the RxE3 Interrupt Enable Register - 1, as indicated
below.
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
COFA
Interrupt
Enable
R/W
0
BIT 3
OOF
Interrupt
Enable
R/W
0
BIT 2
LOF
Interrupt
Enable
R/W
0
BIT 1
LOS
Interrupt
Enable
R/W
X
BIT 0
AIS
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change in Receive LOS Condition
Interrupt
Whenever the XRT74L73 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “Low”.
• It will set Bit 1 (LOS Interrupt Status), within the Rx
E3 Interrupt Status Register - 1 to “1”, as indicated
below.
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