XRT74L73 Datasheet, PDF (174/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
1. The Receive UTOPIA Data bus is configured to be
16 bits wide. Hence, the data, which the Receive
UTOPIA Interface block places on the Receive
UTOPIA Data bus, is expressed in terms of 16-bit
words (e.g., W0–W26).
2. The Receive UTOPIA Interface Block is configured to
handle 54 bytes/cell. Hence, Figure 46 illustrates the
ATM Layer processor reading 27 words (e.g., W0
through W26) for each ATM cell.
In Figure 46 , the ATM Layer processor is initially reading
ATM cell data from the Receive UTOPIA Interface within
UNI #2 (RxUAddr[4:0] = 03h). However, the ATM Layer
processor is also polling the Receive UTOPIA Interface
block within UNI #1 (RxUAddr[4:0] = 01h) and some
“non-existent” device at RxUAddr[4:0] = 1Fh. The ATM
Layer processor completes its reading of the cell from UNI
#1 at clock edge #4. Afterwards, the ATM Layer will cease
to read any more cell data from UNI #1, and will begin to
read some cell data from UNI #2 (RxUAddr[4:0] = 03h).
The ATM Layer processor will indicates its intention to
select a new UNI device for reading by negating the
RxUEn signal, at clock edge #5 (see the shaded portion of
Figure 46 ). At this time, UNI #1 will notice two things:
1. The UTOPIA Address for the Receive UTOPIA Inter-
face block, within UNI #1 is on the Receive UTOPIA
Address bus (RxUAddr[4:0] = 01h).
2. The RxUEn signal has been negated.
UNI #1 will interpret this signaling as an indication that the
ATM Layer processor is going to be performing read oper-
ations from it. Afterwards, the ATM Layer processor will
begin to read ATM cell data from the Receive UTOPIA
Interface block, within UNI #1.
3.4.2.3Receive UTOPIA Interrupt Servicing
The Receive UTOPIA Interface block will generate
interrupts upon the following conditions:
• Change of Cell Alignment (e.g., the detection of
“runt” cells)
• RxFIFO Overrun
• RxFIFO Underrun
If one of these conditions occur and if that particular
condition is enabled for interrupt generation, then
when the local µP/µC reads the UNI Interrupt status
register, as shown below, it should read “xxx1xxxxb”
(where the -b suffix denotes a binary expression, and
the -x denotes a “don’t care” value).
UNI Interrupt Status Register (Address = 05h)
BIT 7
RxDS3
Interrupt
Status
RO
x
BIT 6
RxPLCP
Interrupt
Status
RO
x
BIT 5
RxCP
Interrupt
Status
RO
x
BIT 4
RxUTOPIA
Interrupt
Status
RO
x
BIT 3
TxUTOPIA
Interrupt
Status
RO
1
BIT 2
TxCP
Interrupt
Status
RO
x
BIT 1
TxDS3
Interrupt
Status
RO
x
BIT 0
One Sec Inter-
rupt
Status
RUR
x
At this point, the local µC/µP has determined that the
Receive UTOPIA Interface block is the source of the
interrupt, and that the Interrupt Service Routine
should branch accordingly.
The next step in the interrupt service routine should be
to determine which of the three Receive UTOPIA Block
interrupt conditions has occurred and is causing the In-
terrupt. In order to accomplish this, the local µP/µC
should now read the “RxUT Interrupt Enable/Status
Register, which is located at address 6Bh in the UNI
device. The bit format of this register is presented be-
low.
Address = 6Bh, RxUT Interrupt Enable/Status Register
BIT 7
Unused
RO
BIT 6
RxFIFO Reset
R/W
BIT 5
RxFIFO
Overflw
Interrupt
Enable
R/W
BIT 4
RxFIFO
Underflw Inter-
rupt Enable
R/W
BIT 3
RCOCA
Interrupt
Enable
R/W
BIT 2
RxFIFO
Overflw
Interrupt
Status
RUR
BIT 1
RxFIFO
Underflw Inter-
rupt
Status
RUR
BIT 0
RCOCA
Interrupt
Status
RUR
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