XRT74L73 Datasheet, PDF (25/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
J3
TxOHInd_0/
TxPFrame_0/
TxHDLCDat_6_0
J2
TxOHInd_1/
TxPFrame_1/
TxHDLCDat_6_1
J1
TxOHInd_2/
TxPFrame_2/
TxHDLCDat_6_2
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
O
DESCRIPTION
Transmit Overhead Data Indicator Output/Transmit PLCP Frame Boundary
Indicator Output/Transmit HDLC Controller Data Bit 6 input pin:
The function of these input/output pins depends upon whether the channel
(within the XRT74L73 device) has been configured to operate in the "Clear-
Channel Framer" Mode, the "ATM/PLCP" Mode or the "High-Speed HDLC
Mode.
Clear-Channel Framer Mode - TxOHInd_n:
In the Clear-Channel Framer Mode, this output pin functions as the transmit
overhead data indicator for the local terminal equipment. This output pin is
pulsed "high" for one DS3 or E3 bit period in order to indicate (to the local termi-
nal equipment) that the Transmit Section of the Framer is going to be processing
an overhead bit, upon the next rising edge of TxInClk_n., and will NOT latch the
data that is applied to the TxSer_n input pin. Therefore, when the local terminal
equipment samples the "TxOHInd_n" output pin "high", then it must not apply the
next payload bit to TxSer_n input pin. This output pins serves as a warning that
this particular payload bit is going to be ignored by the Transmit Section of the
Framer, and will not be inserted into payload bits, within the outbound DS3 or E3
data stream.
ATM/PLCP Mode - TxPFrame_n:
If the XRT74L73 device is configured to operate in the ATM UNI/PLCP Mode,
then this output pin will denote the boundaries of "outbound" PLCP frames, as
they are being processed by the Transmit PLCP Processor block. This output
pulses "high" when the last nibble (of a given PLCP frame) is being routed to the
Transmit DS3/E3 Framer block.
NOTE: This output pin is inactive if the XRT74L73 is operating in the "Direct-
Mapped" ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_6_n:
If the channel is configured to operate in the High-Speed HDLC Controller mode,
then the local terminal equipment will be provided with a "byte-wide" Transmit
HDLC Controller byte-wide input interface. This input pin will function as "Bit 6"
within this byte wide interface. Data, residing on the "Transmit HDLC Controller"
byte wide input interface, will be sampled upon the rising edge of the
TxHDLCClk_n output signal.
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