XRT74L73 Datasheet, PDF (33/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
Rx Cell Processor
AD19
AE19
AF19
RxCellRxed_0
RxCellRxed_1
RxCellRxed_2
AF23
AF25
AD26
RxGFC_0/
RxIdle_0
RxGFC_1/
RxIdle_0
RxGFC_2/
RxIdle_0
Y24
RxGFCClk_0
Y25
RxGFCClk_1
Y26
RxGFCClk_2
AB24
AB26
AA25
RxGFCMSB_0
RxGFCMSB_1
RxGFCMSB_2
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
DESCRIPTION
O Receive Cell Processor - Cell Received Indicator:
This output pin pulses "high" each time the Receive Cell Processor receives a
new cell from the Receive PLCP Processor or the Receive DS3/E3 Framer
block.
NOTE: This output pin is only active if the XRT74L73 device has been config-
ured to operate in the ATM UNI Mode.
O Receive GFC Nibble Field - Output Pin/Receive Idle Sequence Indicator:
The exact function of this output pin depends upon whether the XRT74L73
device is operating in the ATM Mode or in the High-Speed HDLC Controller
Mode.
ATM Mode - RxGFC_n:
This pin, along with the RxGFCClk and the RxGFCMSB pins form the "Receive
GFC Nibble-Field" serial output port. This pin will serially output the contents of
the GFC Nibble field of each cell that is processed via the Receive Cell Proces-
sor. This data is serially clocked out of this pin on the rising edge of the RxGFC-
Clk signal. The MSB of each GFC value is designated by a pulse at the
"RxGFCMSB_n" output pin.
High-Speed HDLC Controller Mode - RxIdle_n:
The combination of the RxIdle_n and ValidFCS_n output signals are used to
convey information about data that is being output via the Receive HDLC Con-
troller output Data bus (RxHDLCDat_[7:0]_n).
If RxIdle = HIGH;
The Receive HDLC Controller block with drive this output pin "high" anytime the
flag sequence octet (0x7E) is present on the "RxHDLCDat_[7:0]_n" output data
bus.
If RxIdle_n and ValidFCS_n are both "high"
The Receive HDLC Controller block has received a complete HDLC frame, and
has determined that the FCS value (within this HDLC frame) are valid.
If RxIdle_n is "high" and "ValidFCS_n" is "low"
The Receive HDLC Controller block has received a complete HDLC frame, and
has determined that the FCS value (within this HDLC frame) is invalid.
If "RxIdle_n" is "high" and "ValidFCS_n" is "low"
The Receive HDLC Controller block has received an ABORT sequence.
O Received GFC Nibble Serial Output Port Clock Signal:
This output pin functions as a part of the "Receive GFC Nibble-Field" Serial Out-
put Port; also consisting of the RxGFC_n and RxGFCMSB_n pins. This pin pro-
vides a clock pulse which allows external circuitry to latch in the GFC Nibble-
Data via the RxGFC_n output pin.
NOTE: This output pin is only active if the XRT74L73 device is operating in the
ATM UNI Mode.
O
Received GFC Nibble Field—MSB Indicator:
This output pin functions as a part of the “Receive GFC-Nibble Field” Serial Out-
put port; which also consists of the RxGFC and RxGFCClk pins. This pin pulses
“High” the instant that the MSB (Most Significant Bit) of a GFC Nibble is being
output on the RxGFC pin.
NOTE: This output pin is only active if the XRT74L73 has been configured to
operate in the “ATM UNI” Mode.
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