XRT74L73 Datasheet, PDF (13/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
E23
RxNib_0_0/
RxHDLCDat_0_0
F26
RxNib_0_1/
RxHDLCDat_0_1
H25
RxNib_0_2/
RxHDLCDat_0_2
A26
RxRed_0/
RxNib_3_0/
RxHDLCDat_3_0
E26
RxRed_1/
RxNib_3_1/
RxHDLCDat_3_1
RxRed_2/
G25
RxNib_3_2/
RxHDLCDat_3_2
TYPE
O
O
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
DESCRIPTION
Receive Nibble Interface Output pin - Bit 0/Receive HDLC Controller Data
Bus output pin - Bit 0:
The function of this output pin depends upon whether the channel has been con-
figured to operate in the Clear-Channel/Nibble-Parallel Mode, the High-Speed
HDLC Controller Mode, or in some other mode.
Clear-Channel/Nibble-Parallel Mode - RxNib_0_n:
The channel will output "Received data" (from the remote terminal equipment) to
the local terminal equipment via this pin, along with RxNib_1_n through
RxNib_3_n: This particular output pin functions as the LSB. The data at this pin
is updated on the rising edge of the RxClk_n output signal. Hence, the user’s
local terminal equipment should sample this signal upon the falling edge of
RxClk_n.
High-Speed HDLC Controller Mode - RxHDLCDat_0_n:
This output pin, along with RxHDLCDat_[7:1]_n function as the Receive HDLC
Controller byte wide output data bus. This particular output pin functions as the
LSB (Least Significant Bit) of the Receive HDLC Controller byte wide data bus.
The Receive HDLC Controller will output the contents of all HDLC frames via
this output data bus, upon the rising edge of the "RxHDLCClk_n" output signal.
Hence, the user’s local terminal equipment should be designed/configured to
sample this data upon the falling edge of the "RxHDLCClk_n" output clock sig-
nal.
NOTE: This output pin is only active if the channel is configured to operate in the
"Clear-Channel/Nibble-Parallel" Mode or in the "High-Speed HDLC Controller"
Mode. This output is inactive for all remaining modes.
Receive Section Red Alarm Indicator/Receive Nibble Interface Output pin -
Bit 3/Receive HDLC Controller Data Bus output pin - Bit 3:
The exact function of this output pin depends upon whether the channel has
been configured to operate in the "Clear-Channel Framer/Nibble-Parallel Mode,
the High-Speed HDLC Controller Mode, or in some other mode.
Clear-Channel Framer/Nibble-Parallel Mode - RxNib_3_n:
The channel will output "Received data" (from the remote terminal equipment) to
the local terminal equipment via this pin, along with RxNib_0_n through
RxNib_2_n. This particular output pin functions as the LSB. The data at this pin
is updated on the rising edge of the RxClk_n output signal. Hence, the user’s
local terminal equipment should sample this signal upon the falling edge of
RxClk_n.
High-Speed HDLC Controller Mode - RxHDLCDat_3_n
This output pin, along with RxHDLCDat_[7:4]_n and RxHDLCDat_[3:0]_n func-
tion as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the "RxHDLCClk_n" output signal. Hence, the
user’s local terminal equipment should be designed/configured to sample this
data upon the falling edge of the "RxHDLCClk_n" output clock signal.
Other Modes - RxRED_n:
The Framer/UNI asserts this output pin to denote that one of the following events
has been detected by the Receive DS3/E3 Framer block:
• LOS - Loss of Signal Condition
• OOF - Out of Frame Condition
• AIS - Alarm Indication Signal Detection
14