XRT74L73 Datasheet, PDF (151/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
As far as the XRT74L73 DS3/E3 UNI is concerned,
whether an OAM cell is an F4 or F5 type OAM cell,
is rather unimportant. The Receive Cell Processor circuitry
has been designed to recognize both types of OAM cells,
based upon their header byte pattern. However, whether an
OAM cell is a “Segment type” or an “End-to-End type” is
more important in regards to UNI IC operation. The man-
ner in which the Receive Cell Processor handles “Seg-
ment” and “End-to-End” OAM cells is described below.
3.3.2.4.1Segment Type OAM Cells
Segment type OAM cells are only intended for point-
to-point transmission. In other words, a segment type
OAM cell will be created at a source node, transmis-
sion across a single link, to a destination node; and
then terminated at the destination node. This Segment
OAM cell is not intended to be read or processed by
any other nodes within the ATM Network.
How the Receive Cell Processor handles Segment Type
OAM Cells
The Receive Cell Processor has been designed to
recognize incoming OAM cells, based upon their
header byte pattern. Further, the Receive Cell
Processor is also capable of reading the header byte
patterns, in order to determine if the OAM cell is a
“Segment” type or an End-to-End type OAM cell. If
the incoming OAM cell is a “Segment” type OAM cell,
then the Receive Cell Processor will not write this cell
to the RxFIFO, within the Receive UTOPIA Interface
block and will discard this cell. This act of discarding
the OAM cell terminates it and prevents it from propa-
gating to other nodes in the network.
Note: If the User Cell Filter is configured to pass cells with
header bytes pattern ranges that includes that of the “Seg-
ment”-type OAM Cell, then the User Cell Filter settings will
take precedence and allow the “Segment”-type OAM Cell to
be written to the RxFIFO, within the Receive UTOPIA Inter-
face Block.
Although the Receive Cell Processor will discard this
“Segment” OAM cell, the Receive Cell Processor can
be configured to have the contents of this cell written
into the Receive OAM Cell Buffer, where it can be
read out and processed by the local µP/µC.
If a “1” is written to bit 3 (OAM Check Bit) within the
“RxCP Configuration” register (Address = 4Ch), then
all OAM cells that are received by the Receive Cell
Processor will be written into the Receive OAM Cell
buffer (located at 161h through 1A1h, in the UNI chip
address space).
RxCP Configuration Register (Address = 4Ch)
BIT 7
RxLCD
RO
0
BIT 6
RDPChk
Pattern
R/W
x
BIT 5
RDPChk
Pattern Enable
R/W
x
BIT 4
Idle Cell
Discard
R/W
x
BIT 3
OAM Check
Bit
R/W
x
BIT 2
De-Scramble
Enable
R/W
x
BIT 1
RxCoset
Enable
R/W
x
BIT 0
HEC Error
Ignore
R/W
x
Once the Receive Cell Processor has written the
OAM cell into the “Receive OAM Cell” buffer, then the
Receive Cell Processor will alert the local µP/µC of
this fact, by generating the “Received OAM Cell”
interrupt. If a “0” is written to bit 3 of the “RxCP Con-
figuration” register, then the Receive Cell Processor
will not write the contents of the OAM cells that it re-
ceives, to the “Receive OAM Cell” buffer.
Figure 32 presents an illustration depicting how the
Receive Cell Processor handles incoming Segment-
type OAM cells, if a “1” has been written to bit 3 (OAM
Check Bit) of the “RxCP Configuration” register.
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