XRT74L73 Datasheet, PDF (135/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
If one of these conditions occur, and if that particular
condition is enabled for interrupt generation, then
when the local µC/µP reads the UNI Interrupt Status
UNI Interrupt Status Register (Address = 05h)
BIT 7
RxDS3
Interrupt
Status
RO
BIT 6
RxPLCP
Interrupt
Status
RO
BIT 5
RxCP
Interrupt
Status
RO
BIT 4
RxUTOPIA
Interrupt
Status
RO
Register, as shown below; it should read “x1xxxxxxb”
(where the -b suffix denotes a binary expression, and
the “x” denotes a “don’t care” value).
BIT 3
TxUTOPIA
Interrupt
Status
RO
BIT 2
TxCP
Interrupt
Status
RO
BIT 1
TxDS3
Interrupt
Status
RO
BIT 0
One Sec Inter-
rupt
Status
RUR
At this point, the local µC/µP will have determined
that the Receive PLCP Processor block is the source
of the interrupt, and that the Interrupt Service Routine
should branch accordingly. In order to accomplish this
the local µP/µC should now read the RxPLCP Inter-
rupt Status Register. The bit-format of the RxPLCP
Interrupt Status register is presented below.
RxPLCP Interrupt Status Register (Address = 46h)
BIT 7
RO
BIT 6
RO
BIT 5
BIT 4
Unused
RO
RO
BIT 3
RO
BIT 2
RO
BIT 1
BIT 0
POOF Interrupt Status RLOF Interrupt Status
RUR
RUR
The bit format of the RxPLCP Interrupt Status
Register indicates that only two (2) bit-fields, within
this register, are active. The role of each of these bit
fields follows.
Bit 0—“PLOF Interrupt Status
A “1” in this bit-field indicates that the Receive PLCP
Processor has requested a “Change of PLOF” interrupt.
Note, this type of interrupt could occur due to a transi-
tion in the framing state from the “Out-of-Frame” state
to the “Un-framed” state; during which the RxLOF pin
will toggle “high”. This type of interrupt could also oc-
cur due to a transition from the “Un-framed” state to
the “In-frame” state. It is possible to distinguish be-
tween these two possibilities based upon the read-in
content of the RxPLCP Configuration/Status register. If
the local µC/µP reads in a ‘xxxxx00xb” value from this
register, then the “Change in PLOF” interrupt request
was due to a transition from the “Un-framed” to the
“In-frame” condition. Conversely, if the local µC/µP
reads in the value “xxxxx11xb” then the “Change in
PLOF” interrupt request was due to a transition from
the “Out-of-Frame” state to the “Un-framed” state.
Bit 1—POOF Interrupt Status
A “1” in this bit-field indicates that the Receive PLCP
Processor has requested a “Change of OOF status”
interrupt. Note, this type of interrupt request could oc-
cur due to a transition from the “Un-framed” state to
the “In-frame” state;’ during which the RxOOF pin will
toggle “low”. This type of interrupt could also occur due
to a transition from the “In-frame” to the “Out-of-
Frame” state. It is possible to distinguish between
these two possibilities based upon the read-in content
of the RxPLCP Configuration/Status register. If the lo-
cal µC/µP reads in a “xxxxx0xxb” value from this reg-
ister, then the Receive PLCP Processor has transi-
tioned from the “Un-framed” state to the “In-frame”
state. Conversely, if the local µC/µP reads in
“xxxxx1xxb”, then this indicates the transition from the
“In-frame” state to the “Out-of Frame” state.
Each of these interrupts can be enabled/disabled by
writing the appropriate data to the Receive PLCP In-
terrupt Enable Register. This register has the exact
same bit-format as does the Receive PLCP Interrupt
Status Register. The bit-format of this register is pre-
sented below.
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