XRT74L73 Datasheet, PDF (480/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
Servicing the Change in Receive AIS Condition
Interrupt
Whenever the XRT74L73 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “Low”.
• It will set Bit 0 (AIS Interrupt Status), within the Rx
E3 Interrupt Status Register - 1 to “1”, as indicated
below.
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
COFA
Interrupt
Status
RUR
0
BIT 3
OOF
Interrupt
Status
RUR
0
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
1
BIT 0
AIS
Interrupt
Status
RUR
0
Whenever the user’s system encounters the Change
in Receive AIS Condition Interrupt, then it should do
the following.
1. It should determine the current state of the AIS
condition. Recall, that this interrupt can be gen-
erated, whenever the XRT74L73 Framer IC
declares or clears the AIS defect. Hence, the
user can determine the current state of the AIS
defect by reading the state of Bit 4 (RxAIS) within
the Rx E3 Configuration and Status Register - 2,
as illustrated below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
Rx LOF Algo
BIT 6
RxLOF
R/W
RO
X
X
BIT 5
RxOOF
RO
X
BIT 4
RxLOS
RO
X
BIT 3
RxAIS
RO
X
BIT 2
RxPld Unstab
RO
X
BIT 1
Rx
TMark
RO
X
BIT 0
RxFERF
RO
X
If the AIS Condition is TRUE
1. It should begin transmitting the FERF indication
to the Remote Terminal Equipment. The
XRT74L73 Framer IC automatically supports this
action via the FERF-upon-AIS feature.
If the AIS Condition is FALSE
2. It should cease transmitting the FERF indication
to the Remote Terminal Equipment. The
XRT74L73 Framer IC automatically supports this
action via the FERF-upon-AIS feature.
6.3.6.2.6 The Change in Trail Trace Buffer Mes-
sage Interrupt
If the Change in Trail Trace Buffer Message Interrupt
has been enabled, then the XRT74L73 Framer IC will
generate an interrupt any time the Receive E3 Fram-
er block receives a different Trail Trace Buffer mes-
sage, then it has previously read in.
Enabling and Disabling the Change in Trail Trace
Buffer Message Interrupt.
The user can enable or disable the Change in Trail
Trace Buffer Message interrupt by writing the appro-
priate value into Bit 6 (TTB Change Interrupt Enable)
within the Rx E3 Interrupt Enable Register - 2, as indi-
cated below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
X
BIT 2
BIP-8
Error Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
0
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
0
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