XRT74L73 Datasheet, PDF (211/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
0
d5 d4 d3 d2 d1 d0
0
where ’[d5, d4, d3, d2, d1, d0]’ is the FEAC code
word. The rightmost bit (e.g., a 1) of the FEAC Mes-
sage, is transmitted first. Since each DS3 frame con-
tains only 1 FEAC bit, 16 DS3 Frames are required to
transmit the 16 bit FEAC Code Message.
The XRT74L73 contains the following two registers
that support FEAC Message Transmission.
• Tx DS3 FEAC Register (Address = 0x32)
• Tx DS3 FEAC Configuration and Status Register
(Address = 0x31)
Operating the Transmit FEAC Processor
1
1
1
1
1
1
1
1
In order to transmit a FEAC message to the remote
terminal, the following steps must be executed.
1. Write the 6-bit FEAC code (to be sent) into the Tx
DS3 FEAC Register.
2. Enable the Transmit FEAC Processor.
3. Initiate the Transmission of the FEAC Message.
Each of these steps will be described in detail below.
STEP 1 - Writing in the six bit FEAC Codeword (to
be sent)
In this step, the µP/µC writes the six bit FEAC code
word into the Tx DS3 FEAC Register. The bit format
of this register is presented below.
TX DS3 FEAC REGISTER (ADDRESS = 0X32)
BIT 7
BIT 6
BIT 5
BIT 4
Not Used TxFEAC[5] TxFEAC[4] TxFEAC[3]
RO
R/W
R/W
R/W
0
d5
d4
d3
STEP 2 - Enabling the Transmit FEAC Processor
In order to enable the Transmit FEAC Processor
(within the Transmit DS3 HDLC Controller block) a “1”
BIT 3
BIT2
BIT 1
BIT 0
TxFEAC[2] TxFEAC[1] TxFEAC[0] ^{Not Used}
R/W
R/W
R/W
R0
d2
d1
d0
0
must be written into bit 2 (Tx FEAC Enable) within the
Tx DS3 FEAC Configuration and Status Register, as
depicted below.
TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31)
BIT 7
BIT 6
BIT 5
BIT 4
Not Used
Not Used
Not Used
TxFEAC
Interrupt
Enable
RO
RO
RO
R/W
x
x
x
x
At this point, the Transmit FEAC Processor can be
commanded to begin transmission (See STEP 3).
STEP 3 - Initiate the Transmission of the FEAC
Message
BIT 3
BIT2
BIT 1
BIT 0
TxFEAC
Interrupt
Status
TxFEAC
Enable
TxFEAC
Go
TxFEAC
Busy
RUR
R/W
R/W
R0
x
1
X
X
The transmission of the FEAC code word (residing in
the Tx DS3 FEAC register) can be initiated by writing
a “1” to bit 1 (Tx FEAC Go) within the Tx DS3 FEAC
Configuration and Status register, as depicted below.
TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31)
BIT 7
BIT 6
BIT 5
BIT 4
Not Used
Not Used
Not Used
TxFEAC
Interrupt
Enable
RO
RO
RO
R/W
x
x
x
x
NOTE: While executing this particular write operation, the
binary value “000xx110b” should be written into the Tx DS3
BIT 3
BIT2
BIT 1
BIT 0
TxFEAC
Interrupt
Status
TxFEAC
Enable
TxFEAC
Go
TxFEAC
Busy
RUR
R/W
R/W
R0
x
1
1
X
FEAC Configuration and Status Register. This insures that
a “1” is also being written to Bit 2 (Tx FEAC Enable) of the
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