XRT74L73 Datasheet, PDF (104/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
• “Transmit GFC Nibble-field” serial input port
FIGURE 16. FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT CELL PROCESSOR BLOCK
TUSoC
From TxUtopia ^TCelPresent
TFDat
CellOf52
TxGFC
To/From Pins _TxGFCClk
TxGFCMSB
TFIFORCLK
TFIFORdENB
TDPIntegFail
OAMSent
Controller
TCelRdClk
From Framer/PLCP
TCellCount
TICCount
TxCelTxed
H_PL
HECEn
FIFOrlCDAT[7:0]
GFC[3:0]
HEC
Calculator
HECSoC
HECDat[7:0]
HeaderLoc
TxCPRegSel
DataBusL[7:0]
DataBusH[7:0]
ReadB
WriteB
CSB
Configuration
and Status
Registers
SendOAM
TDPChkPat
ICHECCalcEn
HECInsEn
HECErrMask
CosetIn
GFCInsEn
ICGRegSel[5:0]
ScramblerEn
TxCPInt
To Interrupt
Block
OAMCycle
ICDat[7:0]
Idle Cell
Generator
Scrambler
TCelData[7:0]
OAMDataH[7:0]
OAM
Processor OAMDataL[7:0]
Most of these functional blocks will be discussed in
some detail below. The Transmit Cell Processor will
read in ATM Cell Data from the TxFIFO. The first four
bytes of each cell is loaded into the “HEC Byte calcu-
lator”. The fifth byte of each cell will be read-in and
compared against a pre-defined “Data Path Integrity
Check” pattern. While this “check” is being performed;
the “HEC Byte Calculator” will take these first four
bytes of the cell, and compute a HEC byte value. This
HEC byte value will be written (or inserted) into the
5th octet position of the cell. Consequently, the “Data
Path Integrity Check” pattern will now be overwritten.
Bytes 6 through 53 (the cell payload) of each cell, are
sent onto the “Cell Scrambler” and are summarily
“scrambled”. Afterwards, the cell is reassembled (with
the first four header bytes, the newly computed HEC
byte and scrambled payload), and is routed to the
Transmit PLCP Processor or Transmit DS3 Framer.
When a complete cell is not available in the TxFIFO, a
cell is created by the “Idle Cell Generator”. The user
has the option of specifying the contents of the header
and payload of these Idle Cells via the µP-accessible
registers. The payload of the Idle Cell will be pro-
grammed with a repeating pattern of a byte contained
within an on-chip register. From this point on, the Idle
Cell is processed in the same manner as is an as-
signed (e.g., user or OAM) cell. A valid HEC byte is
computed over the four bytes of the programmed idle
cell header and is inserted into the fifth octet position.
The user has the option to disable the HEC Byte
Calculation and Insertion features for Idle cells, and
the contents of the fifth-header byte programmed reg-
ister may be transmitted directly.
The Transmit Cell Processor provides a means to trans-
mit pre-programmed OAM cells upon demand. The
content of this OAM cell is stored in an on-chip RAM
location, which will be referred to as the “Transmit
OAM Cell Buffer”. When the local µP decides to
transmit the OAM cell to the “Far-End” Terminal, it
writes a “1” to a certain register bit. The Transmit Cell
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