XRT74L73 Datasheet, PDF (119/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
2.3.3.2BIP-8 Generator—B1 Byte
The BIP-8 (Bit Interleaved Parity) generator takes a
total of 12 x 54 octets per PLCP frame, (which con-
sists of the POH byte fields and the associated ATM
cells—a total of 648 octets) and performs a very
specific sequence of calculations. The BIP-8 generator
takes bit 7 (the MSB) of each of the 648 octets and
calculates an even parity bit (based upon these 648
MSB bits). The resulting parity bit is inserted into bit 7
of the B1 byte. This same calculation is also performed
for each of the remaining 7 bits in each octet. The re-
sulting parity bits are grouped together and inserted in-
to the B1 byte field. Therefore, the content of the B1
byte is the result of 8 separate parity bit calculations.
The BIP-8 Calculation results that are obtained based
upon the data within a given PLCP frame, will be in-
serted into the B1 octet position of the very next
PLCP frame.
The B1 byte will ultimately be used by the “Far-End”
Receive PLCP Processor, in order to monitor the
transmission performance between the “Near-End”
Transmitter and the “Far-End” Receiver. For more in-
formation on how the Receive PLCP Processor han-
dles the B1 byte, please see Section 7.2.2.3.1.
2.3.3.3G1 Byte Generator
The purpose of the G1 byte is to provide the “Far-End”
Transmitter with diagnostic information on how well
the “Near-End” Receive PLCP (e.g., the on-chip Re-
ceive PLCP) Processor is receiving and processing its
PLCP frames. The bit field of the G1 byte is
presented below.
BIT 7
BIT 6
BIT 5
Far End Block Error (FEBE)
4 Bits
BIT 4
BIT 3
RAI (Yellow)
1 Bit
BIT 2
BIT 1
BIT 0
X Bits (Ignored by the Receiver)
3 Bits
Each of these bit-fields are discussed below.
Far-End Block Error (FEBE)
The Receive PLCP Processor will receive and extract
the PLCP Overhead bytes from incoming PLCP frames,
originating from a “Far-End” Transmit PLCP Proces-
sor. While the Receive PLCP Processor is receiving a
PLCP frame, it will calculate its own BIP-8 value for
that frame. Afterwards, the Receive PLCP Processor
will then compare its BIP-8 value with the contents of
the B1 byte that it extracts from the very next PLCP
frame. If these two BIP-8 values match, then the Re-
ceive PLCP Processor will reflect this fact by writing a
FEBE value of 0h into a G1 byte. At some phase dur-
ing PLCP frame processing, the Receive PLCP Pro-
cessor will route the contents of the G1 byte to the
Transmit PLCP Processor (on the same chip). This
G1 byte will be packed in the next outbound PLCP
frame, which is in turn routed to the Transmit DS3
Framer. The G1 byte is ultimately transmitted to the
“Far-End” Receive PLCP Processor over the DS3
transport medium, where it will be processed and
evaluated.
If the Receive PLCP Processor determines that the
two BIP-8 values do not match, then the Receive
PLCP Processor will count the number of bit-errors
(e.g., the number of bit-by-bit discrepancies between
these two BIP-8 values) and write this value into the
FEBE nibble of the G1 byte. This G1 Byte will be rout-
ed to the Transmit PLCP Processor, inserted into the
next outbound PLCP frame, and received and pro-
cessed by the Far-End Receive PLCP Processor, as
described above.
Note:
1. Since the BIP-8 value only contains 8-bits, the largest
number of errors that the Receive PLCP processor
can detect is “8”. Therefore, the “FEBE” nibble-field,
within the G1 byte must not contain a value
exceeding the number “8”.
2. For more information on how the Receive PLCP Proces-
sor handles the G1 byte, from the Far-End Transmit
PLCP Processor, please see Section 7.2.2.2.2.
RAI (Yellow Alarm)
If the Receive PLCP Processor has had sufficient
trouble framing to the incoming PLCP frames, (e.g.,
if the Receive PLCP remains “Un-framed” for 2 to 10
seconds), then the Receive PLCP Processor will as-
sert the RAI bit in the G1 byte. The contents of the G1
byte will be routed to the Transmit PLCP Processor
and subjected to the processing that was described
above.
2.3.3.4Inserting Errors into the PLCP Path Over-
head Bytes
The XRT74L73 DS3/E3 UNI has provisions to allow
the insertion of errors into the POH bytes of each out-
bound PLCP frames. This may desireable to do for
chip/equipment test purposes.
The following sections briefly discuss these options.
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