XRT74L73 Datasheet, PDF (130/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
3.2.2.1.2In-Frame (Frame Maintenance Mode)
When the Receive PLCP Processor is operating in
the “In-Frame” mode, it means that it is continually
correctly locating the boundaries of the incoming
PLCP frames. This also enables the Receive PLCP
Processor to perform its tasks of POH byte extraction
and processing. The Receive PLCP processor will in-
dicate its detection of a PLCP frame boundary by
pulsing the RxPFrame output pin “high” at the end of
each frame. Therefore, the pulse rate of this output
pin is nominally 8 kHz. The Receive PLCP Processor
will notify the localµC/µP of its transition from the “Un-
framed” to the “In-frame” state by:
1. Negating both the RxPOOF and RxPLOF output pins
2. Negating both the POOF Status and PLOF Status bits
in the RxPLCP Configuration/Status Register.
3. Generating a “Change of OOF/LOF” status interrupt
request to the local µC/µP.
Additionally, while the Receive PLCP Processor is operat-
ing in the “In-frame” mode, it also will be performing
“Frame Maintenance” functions by continually checking for
and report framing errors. To monitor the number of Fram-
ing Errors that have been detected by the Receive PLCP
Processor read the PMON PLCP Framing Byte Error Count
Registers which are located at Addresses 2Ah and 2Bh.
The bit-formats of these two registers are presented below.
Address = 2Ah, PMON PLCP Framing Byte Error Count Register—MSB
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
FA Error Count—High Byte
RO
RO
0
0
BIT 2
RO
0
BIT 1
RO
0
BIT 0
RO
0
Address = 2Bh, PMON PLCP Framing Byte Error Count Register—LSB
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
FA Error Count—Low Byte
RO
RO
0
0
BIT 2
RO
0
BIT 1
RO
0
BIT 0
RO
0
The contents of these registers reflect the total num-
ber of PLCP Framing Errors that have been detected
since the last read of these registers. These registers
are reset upon read.
3.2.2.1.3Out-of-Frame (OOF) Mode
The Receive PLCP Processor will declare an “Out-of-
Frame” (OOF) condition, if:
• Errors are detected in two consecutive framing
bytes (A1, A2), or
• Two consecutive POIs values are both incorrect.
Once the Receive PLCP Processor declares “OOF”,
then it will enter the “Out-of-Frame” state (per Figure 25 ).
Please note that this mode should not be confused
with the “Un-Framed” mode.
When the Receive PLCP Processor is operating in
the “OOF” mode, it will attempt to re-acquire the
“In-frame” status. However, the Receive PLCP
Processor will continue to use the previous frame
synchronization, while operating in this mode. If the
Receive PLCP Processor cannot re-acquire the
“In-Frame” status after being in the “OOF” mode for
1ms (approximately 8 PLCP frames) or more, then
the Receive PLCP Processor will declare a “Loss of
Frame” and will transition back to the “Un-Framed
Mode”.
The Receive PLCP Processor will indicate its transi-
tion to the “Out-of-Frame” mode by
1. Asserting the RxPOOF pin (Note: the RxPLOF pin
will still remain negated).
2. Asserting the “POOF” status bit in the RxPLCP Con-
figuration/Status Register.
3. Generating a “Change of OOF” status interrupt
request to the local µC/µP.
If the Receive PLCP Processor is able to regain Frame Syn-
chronization, it will negate the RxOOF output pin and
“POOF Status” bit-field in the “RxPLCP Configuration/
Status Register. The Receive PLCP Processor will also
alert the local µP/µC of this occurrence by generating the
“Change in OOF Condition” interrupt.
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