XRT74L73 Datasheet, PDF (87/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
• Detecting and discarding “Runt” cells and insuring
that the TxFIFO can resume normal operation fol-
lowing the removal of the runt cell.
• Insuring that the TxFIFO can respond properly to an
“Overrun” condition, by generating the “TxFIFO Over-
run Condition” interrupt, discarding the resulting “runt”
or errored cell, and resuming proper operation after-
wards.
Transmit UTOPIA FIFO Manager Features
and Options
This section discusses the numerous features that
are provided by the Transmit UTOPIA FIFO Manager.
Additionally, this section discusses how these fea-
tures can be customized to suit particular application
needs.
The Transmit UTOPIA FIFO Manager provides the
following options.
• Handshaking Mode (Octet Level vs Cell Level)
• User selected Operating TxFIFO Depth
• Resetting the TxFIFO
• Monitoring the TxFIFO
2.1.2.3Selecting the Handshaking Mode (Octet
Level vs Cell Level)
The Transmit UTOPIA Interface block offers two
different data flow control modes for data transmission
between the ATM Layer processor and the UNI IC.
These two modes are: “Octet-Level” Handshaking
and “Cell-Level” Handshaking; as specified by the
UTOPIA Level 2, Version 8 Specifications, and are
discussed below.
2.1.2.3.0.1Octet-Level Handshaking
The UNI will be operating in the “Cell-Level” Hand-
shaking Mode following power up or reset. Therefore,
the bit 5 (Handshaking Mode) of the UTOPIA Config-
uration Register to must be set “0” in order to
configure the UNI into the “Octet-Level” Handshake
mode. The main signal that is responsible for data
flow control, between the ATM Layer processor and
the Transmit UTOPIA Interface block is the TxUClav
output pin. The ATM Layer processor is expected to
monitor the TxUClav output pin in order to determine
if it is OK to write data into the TxFIFO. The TxUClav
output pin exhibits a role that is similar to CTS (Clear
to Send) in RS-232 based data transmission systems.
As long as TxUClav is at a logic “high”, the ATM Lay-
er processor is permitted to write more cell data bytes
(or words) into the Transmit UTOPIA Interface block
(and in turn, the TxFIFO). However, when the TxU-
Clav pin toggles “low”, this indicates that the TxFIFO
can only accept 4 (or less) more write operations from
the ATM Layer processor. Once the TxUClav pin re-
turns high, this indicates that the TxFIFO can accept
more than 4 write operations from the ATM Layer pro-
cessor, and that the ATM Layer processor can re-
sume writing data to the Transmit UTOPIA Interface
block.
In other words, if the UTOPIA Data bus is configured
to be 8-bits wide, then the TxUClav signal will toggle
“low” when the TxFIFO can only accept 4 (or less)
bytes of ATM cell data, from the ATM Layer processor.
If the UTOPIA Data bus is configured to be 16-bits
wide; then the TxUClav signal will toggle “low” when
the TxFIFO can only accept 8 (or less) bytes of ATM
cell data from the ATM Layer processor.
Figure 5 presents a timing diagram illustrating the
behavior of TxUClav during writes to the Transmit
UTOPIA Interface block, while operating in the
Octet-Level Handshaking Mode.
FIGURE 5. TIMING DIAGRAM OF TXUCLAV/TXFULLB AND VARIOUS OTHER SIGNALS DURING WRITES TO THE TRANSMIT
UTOPIA, WHILE OPERATING IN THE OCTET-LEVEL HANDSHAKING MODE.
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2
3
4
5
6
7
8
9
10
11
12
TxUClk
TxUClav
TxUEn
TxUData [15:0] _W20 W21 W22 W23 W24 W25
X
X
X
W26 W0 W1
TxUSoC
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