XRT74L73 Datasheet, PDF (176/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
Address = 6Bh, RxUT Interrupt Enable/Status Register
BIT 7
Unused
RO
0
BIT 6
BIT 5
RxFIFO
RxFIFO Reset Overflw Inter-
rupt Enable
R/W
R/W
0
1
BIT 4
RxFIFO
Underflw
Interrupt
Enable
R/W
x
BIT 3
RCOCA
Interrupt
Enable
R/W
x
BIT 2
RxFIFO
Overflw Inter-
rupt
Status
RUR
1
BIT 1
RxFIFO
Underflw
Interrupt
Status
RUR
x
BIT 0
RCOCA
Interrupt
Status
RUR
x
Bit 3—RCOCA Interrupt Enable—Receive UTOPIA
Change of Cell Alignment Interrupt Enable
This “Read/Write” bit-field is used to enable or disables
the generation of interrupts due to a detected
“Change of Cell Alignment” condition, within the
RxFIFO. The local µP/µC can enable this interrupt by
writing a “1” to this bit-field. Upon power up or reset
conditions, this bit-field will contain a “0”. Therefore
the default condition is for this interrupt to be disabled.
Bit 4—RxFIFO Underflw Interrupt Enable—RxFIFO
Underrun Condition Interrupt Enable
This “Read/Write” bit-field is used to enable or disable
the generation of interrupts due to an “RxFIFO Under-
run” condition. The local µP/µC can enable this inter-
rupt by writing a “1” to this bit-field. Upon power up or
reset conditions, this bit-field will contain a “0”. There-
fore, the default condition is for this interrupt to be dis-
abled.
Bit 5—RxFIFO Overflw Interrupt Enable—RxFIFO
Overrun Condition Interrupt Enable
This “Read/Write” bit-field is used to enable or disable
the generation of interrupts due to an “RxFIFO Over-
run” condition. The local µP/µC can enable this inter-
rupt by writing a “1” to this bit-field. Upon power up or
reset conditions, this bit-field will contain a “0”. There-
fore, the default condition is for this interrupt to be dis-
abled.
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