XRT74L73 Datasheet, PDF (111/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PMON Transmitted Idle Cell Count—LSB (Address = 39h)
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
Tx Idle Cell Count—Low Byte
RO
RO
0
0
BIT 2
RO
0
BIT 1
RO
0
BIT 0
RO
0
2.2.2.5Data Path Integrity Check
The Transmit Cell Processor provides for some
performance monitoring of the communication link
between the various UNIs, over the “ATM Switching
System”. This performance monitoring feature is re-
ferred to as the “Data Path Integrity Check”.
The Receive Cell Processor, or some equivalent entity,
within a UNI device, will (after performing HEC byte
verification) write a “Data Path Integrity Check” pattern
into each cell prior to its being read and processed by
the ATM Layer processor. This cell (with the “Data
Path Integrity Check” pattern) will be routed through
the ATM switch, and possibly throughout the Wide Ar-
ea Network (WAN); before arriving to the Transmit
UTOPIA Interface block of a given XRT74L73 DS3/
E3 UNI. The Transmit Cell Processor will read in this
cell from the TxFIFO, and will, prior to inserting a new
HEC byte into the cell, read in the fifth octet from the
TxFIFO and check it for a specific pattern or value.
The Transmit Cell Processor can be configured to
check for either a constant “55h” pattern or an alter-
nating pattern of “55h” and “AAh” for each cell. The
Transmit Cell Processor can also be configured to
generate an interrupt if a Data Path Integrity Test
fails. This can all be can accomplished by writing the
appropriate data to the “TxCP Control” Register (Ad-
dress = 60h). The bit format (with the relevant bit fields
shaded) of this register is shown below.
Note:
1. The “Data Path Integrity Check” feature is disabled
if the Transmit (and Receive) UTOPIA Interface
blocks have been configured to handle 52 byte cells.
2. This “Data Path Integrity Test” is only performed on
user cells. The Transmit Cell Processor does not per-
form this test on OAM or Idle Cells.
TxCP Control Register (Address = 60h)
BIT 7
Scrambler
Enable
R/W
BIT 6
Coset
Enable
R/W
BIT 5
HEC Insert
Enable
R/W
BIT 4
TDPChk
Pattern
R/W
BIT 3
GFC Insert
Enable
R/W
BIT 2
TDPErr Interrupt
Enable
R/W
BIT 1
Idle Cell
HEC CalEn
R/W
BIT 0
TDPErr Interrupt
Status
RUR
The role that each of these “shaded” bit field plays is
presented below.
Bit 4—TDPChk Pat—Test Data Path Integrity Check
Pattern
The Transmit Cell Processor is always checking for a
specific pattern in the fifth octet of a user cell re-
trieved from the TxFIFO. This “Read/Write” bit allows
for specifying the octet pattern that the Transmit Cell
Processor should be checking for. The following table
relates the contents of this bit field to the octet pattern
expected by the Transmit Cell Processor.
TABLE 12: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 4 (TDPCHK PAT) WITHIN THE TXCP CONTROL
REGISTER, AND THE “DATA PATH INTEGRITY CHECK” PATTERN THAT THE TRANSMIT CELL PROCESSOR
WILL LOOK FOR IN THE 5TH OCTET OF EACH INCOMING USER CELL
TDPCHK PAT
0
1
“DATA PATH INTEGRITY PATTERN” EXPECTED BY THE TRANSMIT CELL PROCESSOR
Transmit Cell Processor expects an alternating “55h/AAh” pattern for the value of the fifth octet of the cells
received from the TxFIFO.
Transmit Cell Processor expects a constant “55h” pattern for the value of the fifth octet of the cells received from
the TxFIFO.
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