XRT74L73 Datasheet, PDF (141/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
RxCP Configuration Register (Address = 4Ch)
BIT 7
RxLCD
RO
0
BIT 6
RDPChk
Pattern
R/W
x
BIT 5
RDPChk
Pattern Enable
R/W
x
BIT 4
Idle Cell
Discard
R/W
x
BIT 3
OAM Check
Bit
R/W
x
BIT 2
De-Scramble
Enable
R/W
x
BIT 1
RxCoset
Enable
R/W
x
BIT 0
HEC Error
Ignore
R/W
x
The “HEC Byte Error Correction/Detection”
Algorithm
If the Receive Cell Processor detects one or more
errors in the header bytes of a given cell, then the
“HEC Byte Error Correction/Detection” algorithm will be
employed. The “HEC Byte Error Correction/Detection”
Algorithm has two states: Detection and Correction.
Figure 31 presents a State Machine Diagram of the
“HEC Byte Error Correction/Detection” Algorithm.
Each of these states are discussed below.
FIGURE 31. STATE MACHINE DIAGRAM OF THE HEC BYTE ERROR CORRECTION/DETECTION ALGORITHM
No Error
Detected
Multi-bit Error Detected
(Cell Discarded)
Correction
Mode
No Error Detected
for M consecutive cells
Single-bit Error Detected
(Cell Corrected)
Detection
Mode
Error Detected
(Cell Discarded)
Alpha consecutive cells with incorrect
HEC bytes (to HUNT state)
The “Correction” State
When the “HEC Byte Correction/Detection” Algorithm
is operating in the Correction Mode, cells with single
bit errors (within the header bytes) will be corrected.
However, cells with multiple bit errors are discarded,
unless configured by the user. To configure the Re-
ceive Cell Processor to retain these cells with multi-bit
errors, write to bit 0 (HEC Error Ignore) of the RxCP
Configuration Register, as depicted below.
RxCP Configuration Register (Address = 4Ch)
BIT 7
RxLCD
RO
0
BIT 6
RDPChk
Pattern
R/W
x
BIT 5
RDPChk
Pattern Enable
R/W
x
BIT 4
Idle Cell
Discard
R/W
x
BIT 3
OAM Check
Bit
R/W
x
BIT 2
De-Scramble
Enable
R/W
x
BIT 1
RxCoset
Enable
R/W
x
BIT 0
HEC Error
Ignore
R/W
x
Writing a “1” into this bit-field causes the Receive Cell
Processor to retain errored cells for further processing.
Writing a “0” to this bit-field causes the Receive Cell
Processor to discard those cells with multi-bit errors.
Note: The occurrence of any cells with header byte errors
(single-bit or multi-bit errors) will cause the Receive Cell
Processor to transition from the “Correction” state to the
“Detection” state.
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