XRT74L73 Datasheet, PDF (3/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TABLE OF CONTENTS
1.0 REGISTER MAP OF THE XRT74L73 ................................................................................................. 47
2.0 TRANSMIT SECTION .......................................................................................................................... 82
2.1 TRANSMIT UTOPIA INTERFACE BLOCK .................................................................................................... 82
2.1.1 BRIEF DESCRIPTION OF THE TRANSMIT UTOPIA INTERFACE........................................................................... 82
2.1.2 FUNCTIONAL DESCRIPTION OF THE TRANSMIT UTOPIA INTERFACE .............................................................. 83
2.2 TRANSMIT CELL PROCESSOR .................................................................................................................. 104
2.2.1 BRIEF DESCRIPTION OF THE TRANSMIT CELL PROCESSOR .......................................................................... 104
2.2.2 FUNCTIONAL DESCRIPTION OF TRANSMIT CELL PROCESSOR ...................................................................... 104
2.3 TRANSMIT PLCP PROCESSOR ................................................................................................................. 113
2.3.1 BRIEF DESCRIPTION OF THE TRANSMIT PLCP PROCESSOR .......................................................................... 113
2.3.2 DESCRIPTION OF THE PLCP FRAME AND THE PATH OVERHEAD (POH) BYTES .......................................... 114
2.3.3 FUNCTIONAL DESCRIPTION OF THE TRANSMIT PLCP PROCESSOR BLOCK................................................ 116
2.4 TRANSMIT DS3 FRAMER ............................................................................................................................ 124
2.4.1 BRIEF DESCRIPTION OF THE TRANSMIT DS3 FRAMER .................................................................................... 124
2.5 TRANSMIT E3 FRAMER .............................................................................................................................. 124
2.5.1 BRIEF DESCRIPTION OF THE TANSMIT E3 FRAMER.......................................................................................... 124
3.0 THE RECEIVE SECTION ................................................................................................................... 125
3.1 RECEIVE DS3 FRAMER .............................................................................................................................. 125
3.1.1 BRIEF DESCRIPTION OF THE RECEIVE DS3 FRAMER ....................................................................................... 125
3.2 RECEIVE PLCP PROCESSOR .................................................................................................................... 127
3.2.1 OPERATION OF THE RECEIVE PLCP PROCESSOR ............................................................................................ 127
3.2.2 FUNCTIONAL DESCRIPTION OF THE RECEIVE PLCP PROCESSOR ................................................................ 128
3.3 RECEIVE CELL PROCESSOR .................................................................................................................... 137
3.3.1 BRIEF DESCRIPTION OF THE RECEIVE CELL PROCESSOR ............................................................................. 137
3.3.2 FUNCTIONAL DESCRIPTION OF RECEIVE CELL PROCESSOR......................................................................... 137
3.4 RECEIVE UTOPIA INTERFACE BLOCK ..................................................................................................... 157
3.4.1 BRIEF DESCRIPTION OF THE RECEIVE UTOPIA INTERFACE BLOCK.............................................................. 157
3.4.2 FUNCTIONAL DESCRIPTION OF RECEIVE UTOPIA............................................................................................. 157
4.0 DS3 OPERATION OF THE XRT74L73 .............................................................................................. 178
4.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCIATED OVERHEAD BITS ........................................ 178
4.1.1 FRAME SYNCHRONIZATION BITS (APPLIES TO BOTH M13 AND C-BIT PARITY FRAMING FORMATS)....... 180
4.1.2 PERFORMANCE MONITORING/ERROR DETECTION BITS (PARITY)................................................................. 181
4.1.3 ALARM AND SIGNALING-RELATED OVERHEAD BITS ....................................................................................... 181
4.1.4 THE DATA LINK RELATED OVERHEAD BITS....................................................................................................... 182
4.2 THE TRANSMIT SECTION OF THE XRT74L73 (DS3 MODE OPERATION) .............................................. 182
4.2.1 THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........................................................................... 183
4.2.2 THE TRANSMIT OVERHEAD DATA INPUT INTERFACE ...................................................................................... 200
4.2.3 THE TRANSMIT DS3 HDLC CONTROLLER ........................................................................................................... 211
4.2.4 THE TRANSMIT DS3 FRAMER BLOCK .................................................................................................................. 219
4.2.5 THE TRANSMIT DS3 LINE INTERFACE BLOCK.................................................................................................... 225
4.2.6 TRANSMIT SECTION INTERRUPT PROCESSING................................................................................................. 230
4.3 THE RECEIVE SECTION OF THE XRT74L73 (DS3 MODE OPERATION) ................................................ 233
4.3.1 THE RECEIVE DS3 LIU INTERFACE BLOCK......................................................................................................... 234
4.3.2 THE RECEIVE DS3 FRAMER BLOCK..................................................................................................................... 239
4.3.3 THE RECEIVE HDLC CONTROLLER BLOCK ........................................................................................................ 250
4.3.4 THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE ..................................................................................... 257
4.3.5 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE ........................................................................................ 267
4.3.6 RECEIVE SECTION INTERRUPT PROCESSING.................................................................................................... 274
5.0 E3/ITU-T G.751 OPERATION OF THE XRT74L73 ........................................................................... 288
5.1 DESCRIPTION OF THE E3, ITU-T G.751 FRAMES AND ASSOCIATED OVERHEAD BITS .................... 288
5.1.1 DEFINITION OF THE OVERHEAD BITS.................................................................................................................. 288
5.2 THE TRANSMIT SECTION OF THE XRT74L73 (E3, ITU-T G.751 MODE OPERATION) .......................... 289
5.2.1 THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........................................................................... 289
5.2.2 THE TRANSMIT OVERHEAD DATA INPUT INTERFACE ...................................................................................... 306
5.2.3 THE TRANSMIT E3 HDLC CONTROLLER.............................................................................................................. 315
5.2.4 THE TRANSMIT E3 FRAMER BLOCK..................................................................................................................... 323
5.2.5 THE TRANSMIT E3 LINE INTERFACE BLOCK ...................................................................................................... 328
5.2.6 TRANSMIT SECTION INTERRUPT PROCESSING................................................................................................. 333
5.3 THE RECEIVE SECTION OF THE XRT74L73 (E3 MODE OPERATION) ................................................... 335
5.3.1 THE RECEIVE E3 LIU INTERFACE BLOCK ........................................................................................................... 335
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