XRT74L73 Datasheet, PDF (112/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
The remaining shaded bits are “Interrupt service” re-
lated and will be discussed in the following section.
2.2.2.6Transmit Cell Processor Interrupt Servicing
The Transmit Cell Processor generates interrupts up-
on the detection of an error in the “Data Path Integrity
Check” pattern.
If this condition occurs, and if that particular is en-
abled for interrupt generation, then the UNI will gen-
erate the “Data Path Integrity Check Pattern Error” in-
terrupt. Afterwards, when the local µP/µC reads the
UNI Interrupt Status Register, as shown below; it
should read “xxxxx1xxb” (where the b suffix denotes
a binary expression, and the “x” denotes a “don’t
care” value).
UNI Interrupt Status Register (Address = 05h)
BIT 7
Rx DS3 Inter-
rupt
Status
RO
0
BIT 6
Rx PLCP
Interrupt
Status
RO
x
BIT 5
Rx CP
Interrupt
Status
RO
x
BIT 4
Rx UTOPIA
Interrupt
Status
RO
x
BIT 3
TxUTOPIA
Interrupt
Status
RO
1
BIT 2
TxCP
Interrupt
Status
RO
x
BIT 1
TxDS3
Interrupt
Status
RO
x
BIT 0
One Sec Inter-
rupt
Status
RO
x
At this point, the local µC/µP has determined that the
Transmit Cell Processor block is the source of the in-
terrupt, and that the Interrupt Service Routine should
branch accordingly.
Since the Transmit Cell Processor contains only one
interrupt source, the Interrupt Service Routine, in this
case should perform a read of the “TxCP Control”
Register (Address = 60h) in order to verify and service
this condition. The bit format of this register is
presented below.
Transmit Cell Processor Control Register (Address = 60h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Scrambler
Enable
Coset Enable
HEC Insert
Enable
TDPChk
Pattern
GFC Insert
Enable
R/W
R/W
R/W
R/W
R/W
BIT 2
TDPErr
Interrupt
Enable
R/W
BIT 1
Idle Cell HEC
CalEn
R/W
BIT 0
TDPErr
Interrupt
Status
RUR
This register contain 8 active bit-fields. However, only
two of these bit-fields are relevant to Interrupt
Processing. Bit 0 is an Interrupt Status bit, and Bit 2 is
an Interrupt Enable bit.
Bit 2— TDPErrIntEn—“Test Data Path Integrity
Check” Interrupt Enable
This “Read/Write” bit-field is used to enable or disable
the “Data Path Integrity Check Pattern Error” inter-
rupt. Writing a “0” to this bit-field disables this inter-
rupt. Likewise, writing a “1” to this bit-field enables
this interrupt.
Bit 0—TDPErrIntStat—“Test Data Path Integrity
Check” Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not the “Data Path Integrity Check Pattern Error” in-
terrupt has occurred since the last reading of the “Tx-
CP Control” Register. This interrupt will occur if the
Transmit Cell Processor detects a byte-pattern, in the
fifth octet position of each cell read from the TxFIFO,
that differs from the expected “Data Path Integrity
Check” pattern.
A “1” in this bit-field indicates that this interrupt has
occurred since the last reading of the “TxCP Control”
Register. A “0” in this bit-field indicates that this inter-
rupt has not occurred.
Note: Once the local µP has read this register, Bit 0
(TDPerr Interrupt Status) will be reset to “0”. Additionally,
Bit 3 (TxCP Interrupt Status) within the “UNI Interrupt
Status” register will also be reset to “0”.
2.3Transmit PLCP Processor
2.3.1Brief Description of the Transmit
PLCP Processor
The Transmit PLCP Processor takes the incoming
cells (assigned, Idle, or OAM) from the Transmit Cell
Processor and packs them into PLCP frames. Each of
these PLCP frames also includes various overhead
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