XRT74L73 Datasheet, PDF (42/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
AC15
RxMod_0
AC19
RxPEOP
AC8
TxPEOP
TYPE
O
O
I
DESCRIPTION
Receive PPP Data Bus - Modulus Indicator:
The XRT74L73 device will indicate the number of valid packet octets that are
being read out of the RxPData[15:0] output pins.The XRT74L73 device will drive
this output pin "low" when both bytes (of the RxPData[15:0] data bus) consists of
valid packet data. Conversely, the XRT74L73 device will drive this output pin
"high" when only the upper byte (of the RxPData[15:0] data bus) consists of
valid packet data. The Link Layer Processor is expected to validate all packet
data (that it reads out of the RxPData[15:0] output pins) by also reading the
state of this output pin.
NOTES:This output pin is only active if the XRT74L73 device has been config-
ured to operate in the PPP Mode.
Receive POS-PHY Interface - End of Packet:
The XRT74L73 device drives this output pin "high" whenever the last byte of a
given Packet is being output via the "RxPData[15:0] data bus.
NOTES:
1. This output pin is only valid when the XRT74L73 device is configured to
operate in the PPP Mode.
2. This output pin is only valid when the "Receive POS-PHY Interface -
Read Enable Output pin".
Transmit POS-PHY Interface - End of Packet:
The link layer processor toggles this output pin "high" whenever the Link Layer
Processor is writing the last byte (or word) of a given Packet into the TxP-
Data[15:0] data bus.
NOTES:
1. This input pin is only valid when the XRT74L73 device is configured to
operate in the PPP Mode.
2. This input pin is only valid when the "Transmit POS-PHY Interface -
Write Enable Input pin (TxPEnb*) is asserted.
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