XRT74L73 Datasheet, PDF (133/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PLCP Configuration/Status Register, as depicted be-
low.
RxPLCP Configuration/Status Register (Address = 44h)
BIT 7
x
BIT 6
BIT 5
Unused
x
x
BIT 4
x
BIT 3
Reframe
x
BIT 2
POOF Status
x
BIT 1
PLOF Status
x
BIT 0
Yellow Status
1
Bit 0, within the Receive PLCP Configuration Status
register will be negated when the Receive PLCP Pro-
cessor has received 10 consecutive G1 bytes with
the RAI bit-field being “0”.
Bits 4 through 7—FEBE
This nibble-field represents the number of “BIP-8” bit-
errors that were detected by the “Far-End” Receive
PLCP Processor in a given PLCP frame. Because of
the nature of the BIP-8 value, the FEBE nibble-field
can indicate as many as 8 bit-errors. If the “Near-End”
Receive PLCP Processor receives a G1 byte that
contains a non-zero FEBE value, then the “Near-End”
Receive PLCP Processor will increment the PMON
PLCP FEBE Count Register (Address = 2C, 2D) by
the value of the FEAC nibble-field within the received
G1 byte. The bit-format of these registers is present-
ed below.
Address = 2Ch, PMON PLCP FEBE Count Register—MSB
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
PFEBE Count—High Byte
RO
RO
0
0
BIT 2
RO
0
BIT 1
RO
0
BIT 0
RO
0
Address = 2Dh, PMON PLCP FEBE Count Register—LSB
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
PFEBE Count—Low Byte
RO
RO
0
0
BIT 2
RO
0
BIT 1
RO
0
BIT 0
RO
0
3.2.2.2.3C1 Byte
The Receive PLCP processor will determine the num-
ber of trailer nibbles that exist in a given frame by
reading the contents of the incoming C1 byte which is
the POH byte of the 12th row of a PLCP frame. For a
detailed discussion on the meaning of the C1 Byte,
please see Section 6.3.3.1.
3.2.2.3Extracting PLCP Overhead Bytes via the
Serial Output Port
Once the Receive PLCP Processor declares itself “In-
Frame”, then it will begin to output data via the “Re-
ceive PLCP Processor POH Byte” serial output port.
The “Receive PLCP Processor POH Byte” serial out-
put port consists of the following output pins.
• RxPOH
• RxPOHFrame
• RxPOHClk
Table 22 presents the byte format of the PLCP
frame. The “shaded” bytes represent the data that is
output via the RxPOH pin. Each POH byte is output
with the MSB (most significant bit) first. Each bit, with-
in each of these POH bytes is output on the rising
edge of the RxPOHClk signal. The RxPOHClk signal
has a nominal frequency of 768 kHz. The Receive
PLCP Processor will assert the RxPOHFrame signal
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