XRT74L73 Datasheet, PDF (21/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
D25
RxOOF_0/
RxNib_1_0/
RxHDLCDat_1_0
E24
RxOOF_1/
RxNib_1_1/
RxHDLCDat_1_1
H26
RxOOF_2/
RxNib_1_2/
RxHDLCDat_1_2
R26
RxPOH_0/
RxSer_0
P24
RxPOH_1/
RxSer_1
P25
RxPOH_2/
RxSer_2
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
O
O
DESCRIPTION
Receive Out of Frame Indicator/Receive Nibble Interface Output pin - Bit 1/
Receive HDLC Controller Data Bus Output pin - Bit 1:
The exact function of this output pin depends upon whether the channel has
been configured to operate in the Clear-Channel Framer/Nibble-Parallel Mode,
the High-Speed HDLC Controller Mode, or not.
Clear-Channel Framer/Nibble-Parallel Mode - RxNib_1_n:
The channel will output "Received data" (from the remote terminal equipment) to
the local terminal equipment via this pin, along with RxNib_0_n, RxNib_2_n and
RxNib_3_n: This particular output pin functions as the LSB. The data at this pin
is updated on the rising edge of the RxClk_n output signal. Hence, the user’s
local terminal equipment should sample this signal upon the falling edge of
RxClk_n.
High-Speed HDLC Controller Mode - RxHDLCDat_1_n:
This output pin, along with RxHDLCDat_[7:2]_n and RxHDLCDat_0_n function
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the "RxHDLCClk_n" output signal. Hence, the user’s
local terminal equipment should be designed/configured to sample this data
upon the falling edge of the "RxHDLCClk_n" output clock signal.
All other Modes - RxOOF_n:
The UNI Receive DS3 Framer will assert this output signal whenever it has
declared an "Out of Frame" (OOF) condition with the incoming DS3 frames. This
signal is negated when the framer correctly locates the F- and M-bits and regains
synchronization with the DS3 frame.
Receive PLCP Path Overhead Output pin/Receive Serial Output pin:
The exact function of this output depends upon whether the channel has been
configured to operate in the ATM/PLCP Mode, the Clear-Channel Framer Mode
or not.
ATM/PLCP Mode - RxPOH_n:
This output pin, along with the RxPOHClk_n, RxPOHFrame_n and RxPOHIns_n
pins comprise the "Receive PLCP Frame POH Byte" serial output port. For each
PLCP frame, that is received by the Receive PLCP Processor, this serial output
port will output the contents of all 12 POH (Path Overhead) bytes. The data that
is output via this pin, is updated on the rising edge of the "RxPOHClk_n" output
clock signal. The "RxPOHFrame_n" pin will pulse "high" whenever the first bit of
the Z6 byte is being output via this output pin.
Clear-Channel Framer Mode - RxSer_n:
If the user opts to operate this channel in the "Clear-Channel Framer/Serial"
Mode, then the chip will output all received data, via this output pin. This output
signal will be updated upon the rising edge of RxClk.
NOTE: The user should either configure the channel to operate in the "Gapped-
Clock" Mode, or validate the sampling of each bit (from the RxSer_n output) with
the state of "RxOHInd_n’ output pin, in order to prevent the local terminal equip-
ment from sampling overhead bits.This output pin is only active if the channel
has been configured to operate in the "ATM/PLCP" or the Clear-Channel Framer/
Serial Mode. This pin is inactive for all remaining modes of operation.
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