XRT74L73 Datasheet, PDF (95/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
2.1.2.4.2Multi PHY Operation
The UNI IC will be operating in the “Multi-PHY” mode
upon power up or reset. In the “Multi-PHY” operating
mode, the ATM Layer processor may be writing data
into and reading data from several UNI devices in
parallel. When the UNI is operating in the Multi-PHY
mode, the Transmit UTOPIA Interface block will sup-
port two kinds of operations with the ATM Layer pro-
cessor:
• Polling for “available” UNI devices.
• Selecting which UNI (out of several possible UNI
devices) to write ATM cell data to.
Each of these operations are discussed in the sections
below. However, prior to discussing each of these
operations, the reader must understand the following.
“Multi-PHY” operation involves the use of one (1) ATM
Layer processor and several UNI devices, within a
system. The ATM Layer processor is expected to
TxUTOPIA Address Register (Address = 70h)
BIT 7
RO
0
BIT 6
Unused
RO
0
BIT 5
RO
0
BIT 4
R/W
0
read/write ATM cell data from/to these UNI devices.
Hence, “Multi-PHY” operation requires, at a minimum,
some means for the ATM Layer processor to uniquely
identify a UNI device (within the “Multi-PHY” system)
that it wishes to “poll”, write ATM cell data to, or read
ATM cell data from. Actually, “Multi-PHY” operation
provides an addressing scheme which allows the
ATM Layer processor to uniquely identify “UTOPIA
Interface Blocks” (e.g., Transmit and Receive) within
all of the UNI devices operating in the “Multi-PHY”
system. In order to uniquely identify a given “UTOPIA
Interface block”, within a “Multi-PHY” system, each
“UTOPIA Interface Block is assigned a 5-bit “UTOPIA
address” value. This address value is assigned to a
particular “Transmit UTOPIA Interface block” by writ-
ing this address value into the “TxUTOPIA Address
Register” (Address = 70h) within its “host” UNI de-
vice. The bit-format of the “TxUTOPIA Address Reg-
ister” is presented below.
BIT 3
BIT 2
BIT 1
Tx_UTOPIA_Addr[4:0]
R/W
R/W
R/W
0
0
0
BIT 0
R/W
0
Likewise, a “UTOPIA address” value is assigned to a
particular “Receive UTOPIA Interface block”, within
one of the UNIs (in the “Multi-PHY” system) by writing
this address value into the “Rx UTOPIA Address Regis-
ter” (Address = 6Ch) within the “host” UNI device. The
bit-format of the “Rx UTOPIA Address Register” is
presented below.
Rx UTOPIA Address Register (Address = 6Ch)
BIT 7
RO
0
BIT 6
Unused
RO
0
BIT 5
RO
0
BIT 4
R/W
0
BIT 3
BIT 2
BIT 1
Rx_UTOPIA_Addr[4:0]
R/W
R/W
R/W
0
0
0
BIT 0
R/W
0
Note: The role of the Receive UTOPIA Interface block, in
“Multi-PHY” operation is presented in Section 7.4.2.2.2.2.
2.1.2.4.2.1ATM Layer Processor “polling” of the
UNIs, in the Multi-PHY Mode
When the UNI is operating in the “Multi-PHY” mode,
the Transmit UTOPIA Interface block will automatically
be configured to support “polling”. “Polling” allows an
ATM Layer processor (which is interfaced to several
UNI devices) to determine which UNIs are capable of
receiving and handling additional ATM cell data, at
any given time. The manner in which the ATM Layer
processor “polls” its UNI devices, follows.
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