XRT74L73 Datasheet, PDF (12/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
B16
A16
C15
NAME
TxLev_0
TxLev_1
TxLev_2
G26
EXTLOS_0
G23
EXTLOS_1
F24
EXTLOS_2
TYPE
O
I
DESCRIPTION
Transmit Line Build Enable/Disable Select (to be connected to the TxLev
input pin of the XRT73L03 E3/DS3/STS-1 LIU IC):
These output pins are intended to be connected to the TxLEV input pins of the
XRT73L03 DS3/E3/STS-1 LIU IC. The user can control the state of this output
pin by writing a "0" or a "1" to Bit 2 (TxLEV) within the Line Interface Drive Regis-
ter (Address = 0xXX, 0xXX).If the user commands this signal to toggle "high",
then it will disable the "Transmit Line Build-Out" circuit within the corresponding
channel (of the XRT73L03 LIU IC). In this case, the LIU channel will output
unshaped pulses onto the "Transmit Line signal". In order to insure that the
XRT73L03 LIU IC generates a line signal that is compliant with the Bellcore GR-
499-CORE Pulse Template requirements (as the DSX-3 Cross-Connect) loca-
tion, the user is advised to set this output pin "high" if the cable length (between
the Transmit Output of the LIU Channel and the DSX-3 Cross-Connect) is
greater than 225 feet.
Conversely, if the user commands this signal to toggle "high", then it will enable
the "Transmit Line Build-Out" circuit within the corresponding channel (of the
XRT73L03 LIU IC). In this case, the LIU channel will output shaped pulses onto
the "Transmit Line Signal". In order to ensure that the XRT73L03 LIU IC gener-
ates a line signal that is compliant with the Bellcore GR-499-CORE Pulse Tem-
plate requirements (at the DSX-3 Cross Connect), the user is advised to set this
output pin "low", if the cable length (between the Transmit Output of the
XRT73L03 and the DSX-3 Cross-Connect) is less than 225 feet of cable.
Writing a "1" to Bit 2 of the Line Interface Drive register will cause this output pin
to toggle "high". Writing a "0" to this bit-field will cause this output pin to toggle
"low".
NOTES:
1. The setting for TxLEV has no impact on the shape of the transmit output
pulse if the LIU channel is configured to operate in the E3 Mode.
2. If the designer is not using the XRT73L03 DS3/E3/STS-1 LIU IC, then
this output pin can be used for other purposes.
Receive LOS (Loss of Signal) Indicator Input (from XRT73L03 E3/DS3/STS-
1 Line Interface Unit).
This input pin is intended to be connected to each of the RLOS (Receive Loss of
Signal) output pins of the XRT73L03 DS3/E3/STS-1 LIU IC. The user can moni-
tor the state of this input pin by reading the state of Bit 0 (RLOS) within the Line
Interface Scan Register (Address = 0xXX, 0xXX).
If this input pin is "Low", then it means that the corresponding channel (within the
XRT73L03 device) is currently NOT declaring an LOS condition. However, if this
input pin is "high", then it means that this particular channel is currently declaring
an LOS condition.
For more information on the operation of the XRT73L03 E3/DS3/STS-1 Line
Interface Unit IC, please consult the “XRT73L03 ” data sheet.
NOTE: Asserting the RLOS input pin will cause the XRT74L73 Framer/UNI to
declare an “LOS” (Loss of Signal) condition. Therefore, this input pin should not
be used as a general purpose input.
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