XRT74L73 Datasheet, PDF (236/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
timing information from the incoming DS3 data
stream. Most clock and data recovery schemes rely
on the use of Phase-Locked-Loop technology. One
of the problems of using Phase-Locked-Loop (PLL)
technology for clock recovery is that it relies on transi-
tions in the line signal, in order to maintain lock with
the incoming DS3 data-stream. Therefore, these
clock recovery scheme, are vulnerable to the occur-
rence of a long stream of consecutive zeros (e.g., no
transitions in the line). This scenario can cause the
PLL to lose lock with the incoming DS3 data, thereby
causing the clock and data recovery process of the
receiver to fail. Therefore, some approach is needed
to insure that such a long string of consecutive zeros
can never happen. One such technique is B3ZS (or
Bipolar 3 Zero Substitution) encoding.
In general the B3ZS line code behaves just like AMI
with the exception of the case when a long string of
consecutive zeros occurs on the line. Any 3 consec-
utive zeros will be replaced with either a 00V or a
B0V where B refers to a Bipolar pulse (e.g., a pulse
with a polarity that is compliant with the alternating
polarity scheme of the AMI coding rule). And V refers
to a Bipolar Violation pulse (e.g., a pulse with a polar-
ity that violates the alternating polarity scheme of
AMI.) The decision between inserting an 00V or a
B0V is made to insure that an odd number of Bipolar
(B) pulses exist between any two Bipolar Violation (V)
pulses. The Receive DS3 Framer, when operating
with the B3ZS Line Code is responsible for decoding
the B3ZS-encoded data back into a unipolar (binary-
format). For instance, if the Receive DS3 Framer de-
tects a 00V or a B0V pattern in the incoming pattern,
the Receive DS3 Framer will replace it with three con-
secutive zeros. Figure 84 presents a timing diagram
that illustrates examples of B3ZS decoding.
FIGURE 84. ILLUSTRATION OF TWO EXAMPLES OF B3ZS DECODING
Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
00 V
Line Signal
RxPOS
RxNEG
B 0V
4.3.1.2.3 Line Code Violations
The Receive DS3 LIU Interface block will also check
the incoming DS3 data stream for line code viola-
tions. For example, when the Receive DS3 LIU Inter-
face block detects a valid bipolar violation (e.g., in
B3ZS line code), it will substitute three zeros into the
binary data stream. However, if the bipolar violation
is invalid, then an LCV (Line Code Violation) is
flagged and the PMON LCV Event Count Register
(Address = 0x50 and 0x51) will also be incremented.
Additionally, the LCV-One Second Accumulation
Registers (Address = 0x6E and 0x6F) will be incre-
mented. For example: If the incoming DS3 data is
B3ZS encoded, the Receive DS3 LIU Interface block
will also increment the LCV One Second Accumula-
tion Register if three (or more) consecutive zeros are
received.
4.3.1.2.4 RxLineClk Clock Edge Selection
The incoming unipolar or bipolar data, applied to the
RxPOS and the RxNEG input pins are clocked into
the Receive DS3 LIU Interface block via the RxLi-
neClk signal. The Framer IC allows the user to spec-
ify which edge (e.g, rising or falling) of the RxLineClk
signal will sample and latch the signal at the RxPOS
and RxNEG input signals into the Framer IC. This
feature was included in the XRT74L73 design to in-
sure that the user can always meet the RxPOS and
RxNEG to RxLineClk set-up and hold time require-
ments. This selection is made by writing the appro-
priate data to bit 1 of the I/O Control Register, as de-
picted below.
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