XRT74L73 Datasheet, PDF (84/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
TxUData[15:0] Transmit UTOPIA Data Bus inputs
The ATM Layer Processor will write its ATM Cell Data
into the Transmit UTOPIA Interface block, by placing
it, in a byte-wide (or word-wide) manner on these in-
put pins. The Transmit UTOPIA Data Bus can be con-
figured to operate in the “8-bit wide” or “16-bit wide”
mode (See Section 6.1.2.1.2). If the “8-bit wide” mode
is selected, then only the TxUData[7:0] input pins are
active and capable of receiving data. If the “16-bit
wide” mode is selected, the all 16 input pins (e.g., Tx-
UData[15:0]) are active. The Transmit UTOPIA Data
bus is tri-stated while the active-low TxUEn (Transmit
UTOPIA Data Bus—Write Enable) input signal is
“high”. Therefore, the ATM Layer processor must as-
sert this signal (e.g., toggling TxUEn “low”) in order
write the cell data, on the Transmit UTOPIA Data bus,
into the Transmit UTOPIA Interface Block. The data on
the Transmit UTOPIA Data Bus is sampled and
latched into the Transmit UTOPIA Interface block, on
the rising edge of the Transmit UTOPIA Interface
Block Clock signal, TxUClk.
Additionally, the Transmit UTOPIA Interface block will
only process one cell worth of data (e.g., 52, 53 or 54
bytes, as configured via the CellOf52Bytes option—
See Section 6.1.2.1.3), following the latest assertion
of the TxUSoC (Transmit-Start of Cell) pin. Afterwards,
the Transmit UTOPIA Data bus will become tri-stated
and will cease to process any more data from the ATM
Layer Processor until the next assertion of the TxU-
SoC pin. Once the Transmit UTOPIA Interface block
reaches this condition, it will ignore the assertions of
the TxUEn pin, and will keep the Transmit UTOPIA
Data bus input pins tri-stated until the ATM Layer Pro-
cessor pulses the TxUSoC input pin, once again.
If the Transmit UTOPIA Interface block detects a
“runt” cell (e.g., if the amount of data that is read into
the TxFIFO is less than that configured via the
“CellOf52Bytes” option), then the Transmit UTOPIA
Interface block will discard this cell, and resume nor-
mal operation.
TxUAddr[4:0]—Transmit UTOPIA Address Bus
inputs
These input pins are used only when the UNI is oper-
ating in the Multi-PHY mode. Therefore, for more
information on the Transmit UTOPIA Address Bus,
please see Section 6.1.2.3.2.
TxUClk—Transmit UTOPIA Interface Block Clock
signal input pin
The Transmit UTOPIA Interface block uses this signal
to sample and latch the data on the Transmit UTOPIA
Data bus into the Transmit UTOPIA Address block
(for Multi-PHY operation) into the Transmit UTOPIA
Interface block. This clock signal can run at frequencies
of 25 MHz, 33 MHz, or 50 MHz.
TxUEn —Transmit UTOPIA Data Bus—Write Enable
input
The Transmit UTOPIA Data Bus is tri-stated while this
input signal is negated. Therefore, the ATM Layer
Processor must assert this “active-low” signal (toggle
it “low”) in order to write the byte (or word) on the
Transmit UTOPIA Data Bus, into the Transmit
UTOPIA Interface block.
TxUPrty—Transmit UTOPIA—Odd Parity Bit
Input Pin
The ATM Layer Processor is expected to compute
the odd-parity value of each byte (or word) of ATM
Cell data that it intends to place on the Transmit UTO-
PIA Data bus. The ATM Layer Processor is then ex-
pected to apply this parity value at the TxUPrty pin,
while the corresponding byte (or word) is present on
the Transmit UTOPIA Data Bus.
TxUSoC—Transmit UTOPIA—“Start of Cell”
Indicator
The ATM Layer processor is expected to pulse this
signal “high”, for one clock period of TxUClk, when
the first byte (or word) of a new cell is present on the
Transmit UTOPIA Data Bus. This signal must be kept
“low” at all other times.
Note: Once the ATM Layer Processor has pulsed the TxU-
SoC pin “high”, the Transmit UTOPIA Interface Block will pro-
ceed to read in and process only one cell of data (e.g., 52,
53, or 54 bytes, as configured via the “CellOf52Bytes”
option—See Section 6.1.2.1.3) via the Transmit UTOPIA
Data Bus. Afterwards, the Transmit UTOPIA Interface block
will cease to process any more data from the ATM Layer
Processor until the TxUSoC pin has been pulsed “high”
once again. This phenomenon is more clearly defined in
“Example-1” below.
Further, if the ATM Layer Processor pulses the TxU-
SoC pin before the appropriate number of bytes (as
configured via the “CellOf52Bytes” option—See Sec-
tion 6.1.2.1.3), have been read in and processed by
the Transmit UTOPIA Interface block, then a “runt”
cell will have been detected. Whenever the Transmit
UTOPIA Interface block detects a “runt” cell, it will
generate a “Change in Cell Alignment” interrupt and
will discard the “runt” cell. This phenomenon is more
clearly defined in “Example-2” below.
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