XRT74L73 Datasheet, PDF (19/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
J25
RxLOS_0
J26
RxLOS_1
J23
RxLOS_2
B4
RxNEG_0
C12
RxNEG_1
C17
RxNEG_2
B26
RxOH_0/
RxHDLCDat_6_0
A25
RxOH_1/
RxHDLCDat_6_1
B25
RxOH_2/
RxHDLCDat_6_2
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
O
I
O
DESCRIPTION
Framer/UNI - Loss of Signal Output Indicator:
This pin is asserted when the Receive Section of the channel encounters 180
consecutive 0’s (for DS3 applications) or 32 consecutive 0’s (for E3 applications)
via the RxPOS_n and RxNEG pins. This pin will be negated once the Receive
DS3/E3 Framer has detected at least 60 "1s" out of 180 consecutive bits (for
DS3 applications) or has detected at least four consecutive 32 bit strings of data
that contain at least 8 "1s" in the receive path.
Receive Negative Polarity Data Input:
The exact function of these input pins depend upon whether the XRT74L73
device is operating in the Single-Rail or Dual-Rail Mode.
Single-Rail Mode:
This input pin is inactive and should be pulled to GND, whenever the XRT74L73
device is operating in this mode.
Dual-Rail Mode:
This input pin functions as one of the dual-rail inputs for the incoming B3ZS/
HDB3 encoded DS3 or E3 data, which has been received from an external LIU
IC. RxPOS_n as functions as the other dual-rail input for the Framer/UNI IC.
When this input pin is pulsed "high", it means that the LIU IC has received a
"negative-polarity" pulse from the line.This input signal will be sampled (by the
XRT74L73 device) upon the "user-selected" edge of the RxLineClk_n signal.
Receive Overhead Data Output Interface - output/Receive HDLC Controller
Data Bus - Bit 6 output:
The exact function of this output pin depends upon whether the channel has
been configured to operate in the "Clear-Channel Framer" mode or in the "High-
Speed HDLC Controller" Mode.
Clear-Channel Framer Mode - RxOH_n:
All overhead bits, which are received via the "Receive Section" of the channel
will be output via this output pin, upon the rising edge of "RxOHClk_n".
High-Speed HDLC Controller Mode - RxHDLCDat_6_n:
This output pin, along with RxHDLCDat_[5:0]_n and RxHDLCDat_7_n function
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the "RxHDLCClk_n" output signal. Hence, the user’s
local terminal equipment should be designed/configured to sample this data
upon the falling edge of the "RxHDLCClk_n" output clock signal.
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