XRT74L73 Datasheet, PDF (127/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
Figure 23 presents a simple illustration of the Receive
PLCP Processor block along with the associated
external pins.
FIGURE 23. ILLUSTRATION OF THE SIMPLE BLOCK
DIAGRAM OF THE RECEIVE PLCP PROCESSOR
To Rx Framer
Receive PLCP
Processor
RxPOHClk
RxPOHFrame
RxPOH
RxPFrame
RxPLOF
RxPOOF
3.2.2Functional Description of the Receive PLCP
Processor
The Receive PLCP Processor receives and operates
on data extracted from the payload-portion of the
incoming DS3 data stream (via the Receive DS3
Framer). Once the Receive DS3 Framer reaches the
“In-Frame” state, then the Receive PLCP Processor
will take this incoming data and begin searching for
the PLCP frame boundaries. The Receive PLCP
Processor will inform the “outside world” that it has
began detecting these PLCP frame boundaries by
pulsing the RxPFrame output pin. Figure 24 , presents
a Functional Block Diagram of the Receive PLCP
Processor and Table 19 presents the Byte Format
for a PLCP Frame.
To Rx Cell Processor
FIGURE 24. FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE PLCP PROCESSOR BLOCK
TxPFrame
TxFEBE RdClk
RxFEBE
To/From
TxPLCP Framer
To PMON
From RxDS3
Framer
RxNbDat
RxNbClk
RxPLOF
RxPOOF
OOF Interrupt
LOF Interrupt
FEBE
Bucket
BIP-8 Errors
FA Byte Errors
Frame
Synchronizer
OOF
BIP
Calculator
&
Comparator
OOF/LOF
B1 Byte C1 Byte
C1 Byte
Stuff
Decoder
(Majority Logic)
Overhead Data
NibbleClk
ByteData
Byte
Clock
Over Head
Extractor
to
Serial Port
Nibble/Byte
Converter
Pay Load
Over Head
DeMUX
CellData
Cell Data
Extractor
RxPOH
RxPOHClk
RxPOHFrame
To Pins
RxCellData
RxCellClock
RxCellClockEnable
OOF
To Rx Cell
Processor
RxNbClk
Byte
Clock
Generator
(Divide by 2)
Byte Clock
Column
Counter
(Divide by 57) Column Clock
Row
Counter
(Divide by 12)
Stuff
Counter
(Divide by
13/14)
C1 Byte
Control
Timing & Control
RxPFrame
To
TxPLCP
RxPStuff Framer
128