XRT74L73 Datasheet, PDF (379/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
the Rx E3 Interrupt Enable Register - 2, as indicated
below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
FERF
Interrupt
Enable
R/W
RO
RO
RO
R/W
0
0
0
0
0
BIT 2
BIT 1
BIP-4 Error Framing Error
Interrupt
Interrupt
Enable
Enable
R/W
R/W
0
X
BIT 0
Not Used
RO
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Detection of Framing Error Interrupt
Whenever the XRT74L73 Framer IC detects this in-
terrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “High”.
• It will set the Bit 1 (Framing Error Interrupt Status),
within the RxE3 Interrupt Status Register - 2 as
indicated below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FERF
Interrupt
Status
BIP-4
Error
Interrupt
Status
Framing
Error
Interrupt
Status
Not Used
RO
RO
RO
RO
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Whenever the Terminal Equipment encounters the
Detection of Framing Error Interrupt, it should do the
following.
• It should read the contents of the PMON Framing
Bit/Byte Error Count Registers (located at
Addresses 0x52 and 0x53) in order to determine
the number of Framing errors that have been
received by the XRT74L73 Framer IC.
5.3.6.2.9 The Receipt of New LAPD Message
Interrupt
If the Receive LAPD Message Interrupt is enabled,
then the XRT74L73 Framer IC will generate an inter-
rupt anytime the Receive HDLC Controller block has
received a new LAPD Message frame from the Re-
mote Terminal Equipment, and has stored the con-
tents of this message into the Receive LAPD Mes-
sage buffer.
Enabling/Disabling the Receive LAPD Message
Interrupt
The user can enable or disable the Receive LAPD
Message Interrupt by writing the appropriate data into
Bit 1 (RxLAPD Interrupt Enable) within the Rx E3
LAPD Control Register, as indicated below.
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
RxLAPD
Interrupt Enable Interrupt Enable
RO
RO
RO
RO
RO
R/W
R/W
RUR
0
0
0
0
0
0
0
0
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