XRT74L73 Datasheet, PDF (169/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
different role when the UNI is operating in the Multi-
PHY mode.
The UNI, while operating in Single-PHY mode, can
be configured for either “Octet-Level” or “Cell Level”
handshake modes. In either case, the ATM Layer
Processor is expected to poll the RxUClav pin before
attempting to read in the next byte, word or cell from
the RxFIFO.
3.4.2.2.3.1Multi-PHY Operation
The UNI IC will be operating in the Multi-PHY mode
upon power up or reset. In Multi PHY operating
mode, the ATM layer processor may be pumping data
into and reading data from several UNI devices in
parallel. When the UNI is operating in Multi-PHY mode,
the Receive UTOPIA Interface block will support two
kinds of operations with the ATM Layer processor.
• Polling for “available” UNI devices.
• Selecting which UNI (out of several possible UNI
devices) to read ATM cell data from.
Each of these operations are discussed in the sections
below. However, prior to discussing each of these
operations, the reader must understand the following.
“Multi-PHY” operation involves the use of one (1)
ATM Layer processor and several UNI devices, within
a system. The ATM Layer processor is expected to
read/write ATM cell data from/to these UNI devices.
Hence, “Multi-PHY” operation requires, at a minimum,
some means for the ATM Layer processor to uniquely
identify a UNI device (within the “Multi-PHY” system)
that it wishes to “poll”, write ATM cell data to, or read
ATM cell data from. Actually, “Multi-PHY” operation
provides an addressing scheme that allows the ATM
Layer processor to uniquely identify “UTOPIA Interface
Blocks” (e.g., Transmit and Receive) within all of the
UNI devices, operating in the “Multi-PHY” system. In
order to uniquely identify a given “UTOPIA Interface
Block”, within a “Multi-PHY” system, each “UTOPIA
Interface block” is assigned a 5-bit “UTOPIA Address”
value. The user assigns this address value to a par-
ticular “Receive UTOPIA Interface block” by writing
this address value into the “RxUTOPIA Address Reg-
ister” (Address = 6Ch) within its “host” UNI device.
The bit-format of the “RxUTOPIA Address Register”
is presented below.
Receive UTOPIA Address Register: (Address = 6Ch)
BIT 7
RO
0
BIT 6
Unused
RO
0
BIT 5
RO
0
BIT 4
R/W
0
BIT 3
BIT 2
BIT 1
Rx_UTOPIA_Addr[4:0]
R/W
R/W
R/W
0
0
0
BIT 0
R/W
0
Likewise, the user assigns a “UTOPIA address” value
to a particular “Transmit UTOPIA Interface block”,
within one of the UNIs (in the “Multi-PHY” system) by
writing this address value into the “TxUTOPIA
Address Register” (Address = 70h) within the “host”
UNI device. The bit-format of the “TxUTOPIA
Address Register” is presented below.
Tx UTOPIA Address Register (Address = 70h)
BIT 7
RO
0
BIT 6
Unused
RO
0
BIT 5
RO
0
BIT 4
R/W
0
BIT 3
BIT 2
BIT 1
TxUTOPIA_Addr[4:0]
R/W
R/W
R/W
0
0
0
BIT 0
R/W
0
Note: The role of the Transmit UTOPIA Interface block, in
“Multi-PHY” operation is presented in Section 1.1.2.3.2.
3.4.2.2.3.1.1ATM Layer Processor “polling” of the
UNIs, in the Multi-PHY Mode
When the UNI is operating in the “Multi-PHY” mode,
the Receive UTOPIA Interface block will automatically
be configured to support “polling”. “Polling” allows an
ATM Layer processor (which is interface to several
UNI devices) to determine which UNIs contain ATM
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