XRT74L73 Datasheet, PDF (246/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
FEBE bits (within the outbound DS3 data stream) to a
value other than [1, 1, 1].
How does the Receive DS3 Framer block (within the
XRT74L73) respond when it receives a DS3 frame
with all three (3) of its FEBE bit-fields set to “1”?
As mentioned above, the Terminal Equipment will
transmit DS3 frames, with the FEBE bits set to [1, 1,
1], during un-erred conditions. Hence, if the Receive
DS3 Framer block (within the XRT74L73 Framer IC)
receives DS3 frames with the FEBE bits set to [1, 1,
1] it will interpret this event as an un-erred event, and
will continue normal operation.
However, if the Receive DS3 Framer block receives a
DS3 frame with the FEBE bits set to a value other
than [1, 1, 1], then it will increment the PMON FEBE
Event Count Registers (which are located at address
locations 0x58 and 0x59 within the Framer Address
space).
RXDS3 STATUS REGISTER (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
Reserved
RxFERF
RO
RO
RO
RO
0
0
0
0
4.3.2.5.6 Detection of Change in the AIC State
Section 4.1 indicates that the AIC (Application Identifi-
cation Channel) bit-field is the third overhead bit,
within F-Frame # 1. This particular bit-field is set to
“1” for the C-Bit Parity Framing Format, and is set to
“0” for the M13 Framing Format.
Hence, a given Terminal Equipment receiving a DS3
data stream can identify the framing format of this
DS3 data stream, by reading the value fo the AIC bit-
field. The Receive DS3 Framer block permits the us-
er’s Microcontroller/MIcroprocessor to determine the
state of the AIC bit-field (within the incoming DS3 da-
ta stream) by writing the value of the AIC bit-field,
within the most recently received DS3 frame, into bit
3 (RxAIC) within the Rx DS3 Status Register (Ad-
dress = 0x11), as illustrated below.
BIT 3
RxAIC
RO
0
BIT 2
RO
0
BIT 1
RxFEBE[2:0]
RO
0
BIT 0
RO
0
The Receive DS3 Framer block will also generate an
interrupt if it detects a change of state in the AIC bit-
field (within the incoming DS3 data stream). If this
occurs, then the Receive DS3 Framer block will set
Bit 2 (AIC Interrupt Status) within the Rx DS3 Inter-
rupt Stauts Register (Address = 0x13) to “1” as illus-
trated below.r
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
1
0
0
4.3.2.6 Performance Monitoring of the DS3
Transport Medium
The DS3 Frame consists of some overhead bits that
are used to support performance monitoring of the
DS3 Transmission Link. These bits are the P-Bits
and the CP-Bits.
4.3.2.6.1 P-Bit Checking/Options
The remote Transmit DS3 Framer will compute the
even parity of the payload portion of an outbound
DS3 Frame and will place the resulting parity bit value
in the 2 P-bit-fields within the very next outbound DS3
Frame. The value of these two bits fields is expected
to be the identical.
The Receive DS3 Framer block, while receiving each
of these DS3 Frames (from the remote Transmit DS3
Framer), will compute the even-parity of the payload
portion of the frame. The Receive DS3 Framer block
will then compare this locally computed parity value
to that of the P-bit fields within the very next DS3
Frame. If the Receive DS3 Framer block detects a
parity error, then two things will happen:
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