XRT74L73 Datasheet, PDF (142/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
Monitoring of Single-Bit Errors, during HEC Byte Ver-
ification.
The user can monitor the number of Single Bit Errors
that have been detected by the Receive Cell Processor
during HEC Byte Verification. Each time the Receive
Cell Processor detects a Single-Bit error, the PMON
Received Single-Bit HEC Error Count registers are in-
cremented. These registers are located at addresses
2Eh and 2Fh and their bit-formats are presented below.
PMON Received Single HEC Error Count—MSB (Address = 2Eh)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
S-HEC Error Count—High Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON Received Single HEC Error Count—LSB (Address = 2Fh)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
S-HEC Error Count—Low Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
The contents of these registers reflect the total num-
ber of Single-Bit Errors that have been detected by
the Receive Cell Processor since the last read of this
register. These registers are reset upon read.
Monitoring of Multi-Bit Errors, during HEC Byte Veri-
fication
The user can also monitor the number of Multiple Bit
Errors that have been detected by the Receive Cell
Processor, during HEC Byte Verification by reading the
PMON Received Multiple-Bit HEC Error Count Regis-
ters (Addresses = 30h and 31h). These registers are
incremented once for each incoming cell that contains
multiple (e.g., more than 1) bit-errors. The bit format
of these two registers follow.
PMON Received Multiple-Bit HEC Error—MSB (Address = 30h)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
M-HEC Error Count—High Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON Received Multiple-Bit HEC Error—LSB (Address = 31h)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
M-HEC Error Count—Low Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
The contents of these registers reflect the number of
cells with Multiple-Bit Errors that have been detected
by the Receive Cell Processor, during HEC Byte
Verification, since the last read of this register. These
registers are reset upon read.
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